asynchronous FIFO and its depth

[fragnen]

Suppose there is an asynchronous FIFO with write clock at 200 MHz and read clock at 400 MHz. Suppose the write data is coming with worst burst length of 240. The read clock can read the data at every 2 clock cycles. A FIFO depth can be calculated in usual way in this scenario if the clocks were synchronous. Do we need extra depth for write clock and read clock being asynchronous to each other compared to the depth requirement if write clock and read clock are synchronous to each other? If yes, why?

 

[ads-ee]

This thread looks very familiar...
https://www.edaboard.com/threads/fifo-depth-requirement.396607/#post-1704683

But I'll still give an answer...

If the two clocks are synchronous then a depth of 1 will be sufficient. You can do two valid reads for every write.
If the two clocks are asynchronous then a depth of 3 will probably be enough (depends on how empty/full is synchronized across the clock domains). but you can still manage two valid reads for every write. You just might not start reading for a clock or two due to clock domain crossing.

Don't bother asking me to elaborate, I've seen your other threads.

 

[dpaul]

@ads-ee ,
In thread you have referenced, your answer was the last post, where you agreed that trying to answer fragnen's question is a waste of time (or atlest something like this).