Asynchronous designing in synchronous tools

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roshan12

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Can Xilinx ISE or Altera Quartus synthesize a design unit which uses no clock inputs whatsoever?
Is it possible to simulate an asynchronous module (a microcontroller) using synchronous design tools.??

I tried the fpga synthesis of an asynchronous microcontroller (module in verilog), which very specifically uses no input clocks, in Xilinx as well as Altera. The occurence of errors were eliminated, but certain warnings are definitely changing the desired output.
Xilinx tend to include undesirable variables in its sensitivity list. While Quartus is trying to call some clock unit on its own.

Can someone help me in this regard???..........
 

The clocks appeared because some part of your code behaved like a clock. Also remember that XILINX and altera are not set up to do asynchronous stuff very well. They have async LUTs and synchronous registers, and thats all the logic there is.
Also know that the tools will ignore your sensitivity lists, and build whatever the logic is, not the random behaviour you set up. Quartus will warn you when signals are missing from a sensitivity list.
 
Xilinx tend to include undesirable variables in its sensitivity list. While Quartus is trying to call some clock unit on its own.
Click to expand...
The statement seems to make no sense. What do you mean exactly with "clock unit"?.

I guess, Quartus reports unspecified clocks. If your design is asynchronous and you know how to make a working asynchronous design (do you?) you can just ignore this reports.

An asynchronous design which seems to work in functional (RTL) simulation often fails in real hardware and gate level simulation. In so far I'm curious if you actually know how to manage the asynchronous challenge, not talking about reasonability at the moment.
 

<<< Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" >>>

this statement was appearing in the synthesis info of Altera
Quartus:

alongwith

<<<<<<<<< Info: No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
Info: The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: No clocks to report >>>>>>>>>>>>>>>>

- - - Updated - - -

TrickyDicky said:
The clocks appeared because some part of your code behaved like a clock. Also remember that XILINX and altera are not set up to do asynchronous stuff very well.
Click to expand...

To replace the synchronous mechanism, a request acknowledge handshaking was employed.
The control unit of my uC works based on reponses to the acknowledge signals generated by others blocks. Its fsm works solely based on the acknowledges it receives.
So how can it appear like a clock??
 

because you wrote code that altera synthesis converted to a clock. Do you understand the architecture of an FPGA? the registers in the FPGA need a clock to function. It decided that part of your design could use the registers, hence it created a clock signal from somwhere. Is there any reason you cant have an internal clock? the uC may be asynchronous but there is no reason the FPGA cannot be synchronous.
Why not post the code?
 

The microcontroller consists of a program counter, a Rom, instruction decoder(), alu,registers and Ram.
The control structure is as follows:

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module control_unit ( rst,
                      start,
                      control,
                      path,
                      zero,
                      
                      inc_pc,  
                      req_pc,
                      req_rom,
                      req_idec,
                      req_alu,
                      req_reg,
                      req_ram,
                      req_mux,
                      req_mar,
                      req_r_zero,
                      
                      load_pc,
                      load_acc,
                      load_reg,
                      load_mar,
                      load_r_zero,
                      rw,
                      
                      ack_pc,
                      ack_rom,
                      ack_idec,
                      ack_alu,
                      ack_reg,
                      ack_ram,
                      ack_mux,
                      ack_mar,
                      ack_r_zero,
                      
                      mux_sel );
    
                      
  
 //input [2:0] opcode;                      
 input       rst,start;
 input [1:0] control;
 input       path,zero;
  
 input ack_pc,
       ack_rom,
       ack_idec,
       ack_alu,
       ack_reg,
       ack_ram,
       ack_mux,
       ack_mar,
       ack_r_zero;
       
 output reg inc_pc,
            req_pc,
            req_rom,
            req_idec,
            req_alu,
            req_reg,
            req_ram,
            req_mux,
            req_mar,
            req_r_zero,
            load_pc,
            load_acc,
            load_reg,
            load_mar,
            load_r_zero,
            rw;
            
 output reg [2:0] mux_sel;
            
 parameter state_size=6;           
 
 //_____________STATE CODES___________
  parameter       idle    =0;
  parameter       fet_1   =1;
  parameter       fet_2   =2;
  parameter       fet_3   =3;
  parameter       idec    =4;
  parameter       alu_im  =5;
  parameter       reg2alu =6;
  parameter       reg_1  =7;
  //parameter       acc2reg =8;
  parameter       alu_1   =8;
  
  parameter       load_1=9;
  parameter       load_2=10;
  parameter       load_3=11;
  parameter       load_4=12;
       
  parameter       store_1=13;
  parameter       store_2=14;
  parameter       store_3=15;
  parameter       store_4=16;
    
  parameter       br_1=17;
   
  parameter       brz_1=18;  
  
    
           
 
 
 //_________OPCODES____________
    
    parameter   MOV       = 3'b000;
    parameter   LOAD      = 3'b001;
    parameter   STORE     = 3'b010;
    parameter   AND       = 3'b011;
    parameter   OR        = 3'b100;
    parameter   XOR       = 3'b101;
    parameter   SUB       = 3'b110;
    parameter   ADD       = 3'b111;   
 
 
reg [state_size-1:0] state,next_state;
 
 
//__________________________________________________________________________________
always @ (start or 
          rst or 
          posedge ack_pc or 
          posedge ack_rom or 
          posedge ack_idec or 
          posedge ack_mux or 
          posedge ack_alu or 
          posedge ack_reg or 
          posedge ack_ram or 
          posedge ack_mar or 
          posedge ack_r_zero)
begin
  
  if(rst==0 && start==1)
    begin
     state<=idle; 
     
            req_mux=0;
            req_pc=0;
            req_rom=0;
            req_idec=0;
            req_alu=0;
            req_reg=0;
            req_ram=0;
            req_mar=0;
            req_r_zero=0;
            
            load_pc=0;
            load_acc=0;
            load_reg=0;
            load_mar=0;
            load_r_zero=0; 
            rw=0;
    end
 
  else if(start==1 && rst==1)
    begin
    state<=next_state;
    end
    
  else
    begin
     req_pc=0; req_rom=0; req_idec=0; req_alu=0; req_reg=0; req_ram=0; 
     load_pc=0; load_acc=0; load_reg=0;
             state<=idle;
    end
    
end
//_______________________________________________________________________________________
 
 
//_______________________________________________________________________________________ 
 always @ (state)
 begin
      
   case (state)
     
     idle: next_state=fet_1;
     
     fet_1: begin
            next_state=fet_2;
            
            req_mux=0; //req_pc=0; 
            req_rom=0; 
            req_idec=0; 
            req_alu=0; 
            req_reg=0; 
            req_ram=0;
            req_mar=0;
            req_r_zero=0;
             
            load_pc=0; 
            load_acc=0; 
            load_reg=0;
            load_mar=0;
            load_r_zero=0;
            
            rw=0;
            req_pc=1; end 
            
     fet_2: begin
            next_state=fet_3;
            load_pc=0;
            inc_pc=1;
            req_pc=0; 
            
            req_rom=1; end
            
     fet_3: begin 
            next_state=idec;
            
            req_rom=0; 
            req_idec=1; end   
                    
     idec: begin
           req_idec=0;
           
           if(path)
             begin
               case(control)
                 2'b00: begin
                        next_state=load_1; 
                        mux_sel=00;
                        req_mux=1; end
                        
                 2'b01: begin
                        next_state=br_1;
                        mux_sel=00;
                        req_mux=1; end
                        
                 2'b10: begin
                        next_state=brz_1;
                        load_r_zero=1;
                        req_r_zero=1; end
                        
                 2'b11: begin 
                        next_state=store_1;
                        mux_sel=00;
                        req_mux=1; end
                        
                 default: req_mux=0;
               endcase
             end
           
           
           else
           begin      
             case(control)
            2'b00: begin 
                   mux_sel=00; next_state=alu_im; 
                   req_mux=1; end
            2'b01: begin 
                   mux_sel=10; next_state=reg2alu; 
                   req_idec=0; 
                   req_reg=1; end
            2'b10: begin 
                   mux_sel=00; next_state=reg_1;
                   req_mux=1; end
            2'b11: begin 
                   mux_sel=01; next_state=reg_1; 
                   req_mux=1; end
            default:begin
               req_mux=0; 
                   end
             endcase
           end
           end
           
           
     alu_im: begin 
             next_state=fet_1; load_acc=1; 
             req_mux=0; 
             req_alu=1; end
             
     reg2alu: begin 
              next_state=alu_1; 
              req_reg=0; 
              req_mux=1; end
              
     reg_1: begin 
             next_state=fet_1; load_reg=1; 
             req_mux=0; 
             req_reg=1; end
             
                 
     alu_1: begin 
            next_state=fet_1; load_acc=1; 
            req_mux=0; 
            req_alu=1; end
      
      load_1:begin
                  next_state=load_2; 
                  req_mux=0;
                  load_mar=1;
                  req_mar=1; end
      load_2:begin
                  next_state=load_3;
                  req_mar=0;
                  rw=0;
                  req_ram=1; end
      load_3:begin
                  next_state=load_4;
                  req_ram=0;
                  mux_sel=11;
                  req_mux=1; end
      load_4:begin
                  next_state=fet_1;
                  req_mux=0;
                  load_reg=1;
                  req_reg=1; end
      
      
    
      store_1:begin
                  next_state=store_2;
                  req_mux=0;
                  load_mar=1;
                  req_mar=1; end
      store_2:begin
                  next_state=store_3;
                  req_mar=0;
                  req_reg=1; end
      store_3:begin
                  next_state=store_4;
                  req_reg=0;
                  mux_sel=10;
                  req_mux=1; end
      store_4:begin
                  next_state=fet_1;
                  req_mux=0;
                  rw=1;
                  req_ram=1; end
      
  
      br_1:begin
            next_state=fet_2;
            req_mux=0;
            inc_pc=0;
            load_pc=1;
            req_pc=1; end
            
      brz_1:begin
            req_r_zero=0;
            load_r_zero=0;
            if(zero)
              begin
              next_state=br_1;
              mux_sel=00;
              req_mux=1;
              end
            else
              begin
              next_state=fet_1;
              req_mux=1;
              end
            end     
                
     default: begin
       req_mux=0;
             end
    
   endcase
 end
 
 endmodule
 
Last edited by a moderator:

posedge ack_pc or
posedge ack_rom or
posedge ack_idec or
posedge ack_mux or
posedge ack_alu or
posedge ack_reg or
posedge ack_ram or
posedge ack_mar or
posedge ack_r_zero
Click to expand...

There is your clock. Any posedge statements like this will be treated as a clock. So in your case it will have or'd all the signals and then taken the output as a clock. For truely asyc design, you cannot do this.
 
Sir, in our fsm design there appears to be a warning appearing while xilinx synthesis. The warning reads as:
"Signal <next_state> is missing in the sensitivity list is added for synthesis purpose"

I guess its pretty clear that the trouble with clock appears only in the 1st "always" sensitivity list and the second "always" block consists only of the state parameters.

Then if the next_state parameter comes in the 1st always block then the fsm will function undesirably.... Doesn't it????
 

Synthesis ignores sensitivity lists and creates the logic from the code only. Hence if you miss signals out of a sensitivity list you may have a missmatch between the simulation and hardware behaviour, with the simulation being incorrect. It is refering to your "clocked" process (discussed above) - as Xilinx as decided its not really a clocked process. As state is assigned from next state, next state should be in the sensitivity list.
 

The syntax of the first always block event list completely contradicts the rules for synthesizable Verilog. You can refer to IEEE Std 1364.1 (IEEE Standard for Verilog Register Transfer Level Synthesis) or user manuals of various synthesis tools. Neither multiple edge sensitive events nor the mixture of edge and level sensitive events are supported. The only exception is the usage of additional edge sensitive statements to model asynchronous inputs of edge sensitive storage elements. Also in this case, there will be only one signal (= clock) that triggers edge sensitive events.

The code in post #6 has also lots of "multiple driver" errors, although you claimed that you did resolve the errors.
 
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