asynchronous Counter mod 12 D

[darthachill]

Hi everybody,

today I have a problem conected with design asynchronous Counter mod 12 D.

I use OR4 to detect for a while state "1111", because I want to reset counter to state "1101", but it's not working...
On symulation we can see that Counter reset his state after detected state "0111", before was state"1000", so counter detected it as state "1111" because it's asynchronous.
How can I solve this problem?







I should like to express my thanks for your support.

 

[andre_luis]

In you simulation, it is supposed a zero delay for each gate, or intermediary states shouldn't be taken in account ?

 

[ads-ee]

The AND gate output can't be combinational as it will glitch due to the delayed caused with each FF as you are using them in a ripple count fashion. If you don't want glitches the AND gate output will need to be registered, which requires that the delay from the first FF to the last FF and the setup time of the AND gate FF are less than the clock frequency. I suspect this will be a slower circuit than the usual synchronous counter implementation.