ASYNC OR SYNC RESET? which one is use more in ASIC industry?

Hi,

i have recently moved from FPGA to ASIC and have realised that most of the ASIC designs in my new company use asynchronous reset. I find this quite different from what is generally done in FPGA.
In FPGA synchronous reset designs are recommended by the vendors (xilinx/altera) as they have fpga fabric with built-in sync reset logic in registers.

i would like to know is it a general practice in the industry to use async reset for ASIC designs or is it just in my company?

i know that asic libraries have asyc resetable ffs.
in my company all the ffs used are resetable, even for registers in data path, is it also common to use same type of ff for the whole design?

also can somebody tell me if vendors also provide libraries with ffs having built in sync reset logic? or if sync reset is always synthesised outside of flipflop in ASIC ?

-abhinavpr

In FPGA synchronous reset designs are recommended by the vendors (xilinx/altera) as they have fpga fabric with built-in sync reset logic in registers.

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Don't agree. Most FPGA designs are using a synchronously released asynchronous reset.

Async reset with sync release is probably the most common. Sync reset is used occasionally though. Async has the obvious advantage that your PoR works before the clock is working. You need a sync release to avoid potential metastability and make sure FSM start in a consistent state.

Resetting all FFs is a waste of area. Someone probably has heard some myth about DFT or X propagation.

Another benefit of async reset is for logic driven by gated clock, you don't need clock running to clear the logic.

how do you deal with glitches in async resets? in sync reset , a glitch can only affect it if it happens close to clock edge but in async reset any glitch can assert reset which can be really dangerous. how can you make sure that a glitch will not affect ongoing process?

"Resetting all FFs is a waste of area. Someone probably has heard some myth about DFT or X propagation."

do you mean that asic library consists of two types of ffs one asynchronously resettable and other non-resetable?

abhinavpr said:

do you mean that asic library consists of two types of ffs one asynchronously resettable and other non-resetable?

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It depends on the library, but yes, there will usually be FFs without resets that are smaller than those that do have a reset.

In asic there is no synchronous reset, synchronous reset, means the reset signal is included in the data path to the D pin, and at least one clock cycle is required to capture this value.

For gated clock, that's does not changed any think, except the reset need to be included in the clock enable, and the chip will have all flops working during the reset time, which is not "great" in term of power consumption.

The asynchronous signal need to be clean and generated from a analog component.

As already mentioned by jbeniston, the reset is asynchronous but the reset is released on the opposite edge of the flop itself, I means a flop clock with a rising edge will received a reset released on the falling edge to avoid any race between the two edges.

rca said:

In asic there is no synchronous reset, synchronous reset, means the reset signal is included in the data path to the D pin,

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Not necessarily.

rca said:

The asynchronous signal need to be clean and generated from a analog component.

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You can generate async resets from internal digital logic. The main consideration is allowing them to be disabled during scan.

Good paper here: **broken link removed**

jbeniston said:

Async reset with sync release is probably the most common. Sync reset is used occasionally though. Async has the obvious advantage that your PoR works before the clock is working. You need a sync release to avoid potential metastability and make sure FSM start in a consistent state.

Resetting all FFs is a waste of area. Someone probably has heard some myth about DFT or X propagation.

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Resetting all FF's in a FPGA is not a waste of area at all. Most FPGA's come with a built in global asynchronous reset for free. It is called the CONFIG pin. You assert the pin and it puts all of the FF's into a known reset state before the clock starts. That is why you don't use FF's with an asynchronous reset in an FPGA because you don't need two complete asynchronous reset systems.

You do have to add it if you want to use your code for an asic. That is what the OP was referring to.


Do not worry about saving gates. Gates today are to cheap to meter. If you want the lowest cost solution to any problem then the answer will usually be to throw gates at it. We put a reset on every flop because its cheaper to do that than it is to verify that the design works if you don't have a reset on every flop. In todays world verification time is a bigger problem than gate count.

The big problem that many designers make is that they mix their synchronous and asynchronous resets together to drive the async reset port on the FF. If you create a synchronous soft reset signal for each module and gate that with the asynchronous power on reset signal then you are opening a pandoras box of timing and DFT problems. Not only do you need DFT logic for scan to work but if you ever reset that module without resetting the modules that are driven from that module then you have added a new and slower timing path to all your critical paths.

jt_eaton said:

Resetting all FF's in a FPGA is not a waste of area at all.

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I was talking about for ASICs.

jt_eaton said:

You do have to add it if you want to use your code for an asic.

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Nope.

jt_eaton said:

We put a reset on every flop because its cheaper to do that than it is to verify that the design works if you don't have a reset on every flop.

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It's no different.

thanks everybody for the replies. it seems that asynchronous resets are more common in ASIC designs but it is still unclear whether only async resetable flops are used or both async and sync resets are used in design. like in my company async flops for control path and sync reset flops for datapath.

my query is more about what is general practice in asic industry rather than the merits or demerits of using them, although the discussion about merit and demerits is very helpful.

You will find different companies use different approaches, depending upon what folklore their employees believe. I've seen chips made with most permutations of the styles discussed (including those that aren't reliable :-D), but I'd say async reset / sync release is probably the most common.

abhinavpr said:

thanks everybody for the replies. it seems that asynchronous resets are more common in ASIC designs but it is still unclear whether only async resetable flops are used or both async and sync resets are used in design. like in my company async flops for control path and sync reset flops for datapath.

my query is more about what is general practice in asic industry rather than the merits or demerits of using them, although the discussion about merit and demerits is very helpful.

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What you will need to do is find out who has the engineering responsibility for the reset system and ask them what to do. Its actually that simple. The problem is that ER not held by IC designers it is held by PCB designers. Board designers create the power on reset circuit and route it to all of the IC's. Most of the time it goes to the IC but in the case of some chips like memories that do not have a reset they route through the controller IC. They also design the filtering and shielding to keep noise out of the reset system. All IC designers do is to create a subblock that the PCB designers weave into the products reset system.

If you were to talk to these people then you would discover that there is a complete disconnect between what board designers want and what IC designers are delivering for a reset system. IC designers are all focused on making sure that when you push the reset button that it goes to all FF's and cannot be blocked by anything. PCB designers are focused on making sure that the product does not reset due to an ESD event. They have to block the reset for a long enough time to determine if it is a real request or noise. Most IC's provide an asynchronous reset system with no way to block the signal other than on the PCB.

IC designers are like the guy working on the first death star who was given the task of building the thermal emergency exhaust port. He was so engaged in making sure that there was clear passage between the core and the surface for any reactor event that he failed to realize that the primary need of a warship was that you didn't have clear passage when you weren't having a reactor event.

Well the majority of the chip has made since 10years did not have any RESET pads, always from an internal module. Our chip is the master chip of the system, and our customers do not need to add extra components to reset any chips on their PCB.

Even I made the transition from the FPGA to the ASIC industry and I also noticed the same thing. I was working on really high speed designs when I was into ASIC. In synchronous resetSo systems, you have an additional component coming in the data path if your library has async reset flops. As it was a timing critical design, I suspect they wanted a clean data path and thus chose an async reset system. So meeting timing might be a consideration to decide..

rca said:

Well the majority of the chip has made since 10years did not have any RESET pads, always from an internal module. Our chip is the master chip of the system, and our customers do not need to add extra components to reset any chips on their PCB.

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Your chip is only the master in mission mode. What about test? You still need to provide some reset input for the chip tester. How about simulations? You can design your clock generators so they self start without a reset but you still need one for simulations.

For the simulation, the analog model, emulate the power-on-reset.
For test, one pad becomes a reset control for the scan.

rca said:

For the simulation, the analog model, emulate the power-on-reset.
For test, one pad becomes a reset control for the scan.

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And how does your chip know that it is in test mode?

You have to have at least one input pad to tell the chip that it is either in mission mode or test mode. Jtag has become the standard way to access test features and using its test reset pin will serve this function. Your product will have a pull down on this pad so that you know that all test features are held in reset until you attach a tester to that pin.


Does your chip have analog voltage comparators generate the power-on-reset ? Running the raw output of any sensor into something as crucial as the reset system usually requires digital filtering. How do you reset the filters for your sims?

jt_eaton said:

You have to have at least one input pad to tell the chip that it is either in mission mode or test mode. Jtag has become the standard way to access test features and using its test reset pin will serve this function. Your product will have a pull down on this pad so that you know that all test features are held in reset until you attach a tester to that pin.

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There are many ways to do this. You don't need dedicated test pads or JTAG. Quite a few ICs out there that need to minimize pin count will enter test mode via an I2C or SPI accessible register, which resets via an async reset from the PoR to functional mode.