Yaro
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Can someone advice me an already written Asynchronous FIFO (2 Clock FIFO) code in VHDL, possibly already used without problems?
All the codes I've found generate me some errors. My FPGA manufacturer FIFO's when I try to read and write at the same time it create me problems in simulation and also I can't modify it or adapt to another FPGA.
I need the possibilty to read and write at the same time with 2 different clocks without clock coincidence errors.
All the codes I've found generate me some errors. My FPGA manufacturer FIFO's when I try to read and write at the same time it create me problems in simulation and also I can't modify it or adapt to another FPGA.
I need the possibilty to read and write at the same time with 2 different clocks without clock coincidence errors.