Asymmetric Duty Cycle of Clock after CTS ( on time & off time are not same )

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Have a question on duty cycle of clock.

Let’s say after CTS clock duty cycle is not 50% i.e. Ton = 70% & Toff = 30% (on time of clock is more than off time),
now in that case
1. what are the issues we’ll face
2. what violation we’ll face w.r.t timing?

(I know that synchronization will not perfect)

Kindly share your thoughts/real experience.. Thanks..
 

1- do you have rise to fall or fall to rise paths? If not, you don't care of the duty cycle. if yes, you will less time to respect the setup time, to improve you synthesis and placement, you could modelise your clock to follow the expected clock tree result.
2- synchronisation care of the duty cycle only if the synchronisation used the two edges, and also you have two clock domains and so two clock trees?
 
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    ro9ty

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Thanks rca for sharing your inputs.

I am more interested to know how it is going to affect setup & hold. If I try to analyze it on paper with traditional 2 flops & one combo sandwiched - I am seeing no issues with setup & hold - but don't know whether I am making any mistake.

2. Very keen on transition time of cell (buffer), from where this clock is passing... Not able to analyze it...

Can you share your insights?
 

The duty cycle impact the setup if you have rise to fall or fall to rise paths, because you have less time between the two edges.
 

rca said:
The duty cycle impact the setup if you have rise to fall or fall to rise paths, because you have less time between the two edges.
Click to expand...

Not clear for me - can you elaborate it pls. Thanks.

- your clock freq is same - but duty cycle varies - then in that case - two posedge tick will be at same time - even though your duty cycle differs
- What you mean by rise to fall & fall to rise path??
 

path startting with a rising edge flop and finishing with a flop clocked by the falling edge path, (and inverse) in this case the duty cycle is important for the setup.
 

Assume your clock freq is 20MHz -> period 50ns. 70% is rise =35ns and 30% fall =15ns.
Assume 2 flops are there A and B both triggered by same clock. A launches clock with leading edge an B captures it with next leading edge. Now as you already know setup is calculated in next clock cycle so B will capture it and check for setup when the next clock leading edge arrives (rise to rise path). Let us say A launches at 0ns and B captures at 50ns.
Then your Required time is 50ns (assume no latency in clock path) and let us take Arrival time (data time) as 38ns. Therefore slack = RT-AT = 50 - 35 = 15ns so no violation. It does not matter where your fall edge comes. In this case the point is that the next rising edge comes at 50ns.
.
Now say A launches at leading edge but B captures at falling edge (rise to fall path). Arrival time is same 35ns, but now Required time = 35ns (since this is where the clock falls 70% duty cycle) So slack = RT -AT =35-35 =0 Just escaped the violation but imagine if the duty cycle would have been 50%-50% the falling edge would have come at 25ns. Thus slack would be = 25 -35 =-10 and it would violate.:roll::evil:
 
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    pdude

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Nice explanation. Thanks !!
 

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