asymetric delay on high speed bus

[MZanders]

i'm running a 66MHz (15ns period) bus which needs to interface to some devices. Some have rather slow requirements regarding adress setup and NRD/NWR to NCS setup times.
So: the falling edge of the NRD and NWR should be delayed for about one clock cycle, but the rising edge should stay right where it is now (only 2ns margin).
Any ideas? I started thinking about putting some flipflop in there but I can't get it right...

 

[brmadhukar]

Hi,
Will not a simple divide by two circuit work?
B R M

 

[MZanders]

i'm afraid not
if dividing only the NRD line by 2, waveforms are totally messed up and nothing will work. Dividing all of the bus lines by two would require for instance two actions for each operation... if it ever works at all