eeStud
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Hi,
When i am running Assura LVS i am getting mismatch between layout & schematics regarding the top cell pins (the pins are at the beggining of the top cell SUBSET definition in the cdl file).
How can i prevent this mismatch?
Thanks.
When i am running Assura LVS i am getting mismatch between layout & schematics regarding the top cell pins (the pins are at the beggining of the top cell SUBSET definition in the cdl file).
How can i prevent this mismatch?
Thanks.