ashwatik
Newbie level 3
- Joined
- May 9, 2011
- Messages
- 4
- Helped
- 0
- Reputation
- 0
- Reaction score
- 0
- Trophy points
- 1,281
- Activity points
- 1,320
As far as I have scoured the internet and this forum, I have not found this particular question, and this is my first post on this forum, forgive me (and correct me) if I have posted this in error.
I have a question about the substrate connection in the AMS 0.35u process for the Bondpad with primary and secondary ESD protection. I am not sure how to make the appropriate substrate connection in order to get the design LVS clean. I am just trying to understand the bondpad structure at this point, I need to make the bondpad array once I figure this out. I have uploaded a single bondpad with a resistor connected to it and two pins. The LVS will show a pin mismatch error, that is okay for now.
Problem: Layout is not LVS clean, have not run DRC yet. Attached (i) LVS out text file (detects more diodes in layout than in schematic), (ii) schematic (iii) subcell schematic (iv) layout images
Note 1: I have used inherited connections to change the "vdd3o", "vdd3r", "gnd3o" and "gnd3r" to find "vd" and "vs" in the bondpad subcell.
Note 2: I tried adding PD_C vias, but I am not sure if I am doing that correctly.
View attachment lvs_output.txt
I have a question about the substrate connection in the AMS 0.35u process for the Bondpad with primary and secondary ESD protection. I am not sure how to make the appropriate substrate connection in order to get the design LVS clean. I am just trying to understand the bondpad structure at this point, I need to make the bondpad array once I figure this out. I have uploaded a single bondpad with a resistor connected to it and two pins. The LVS will show a pin mismatch error, that is okay for now.
Problem: Layout is not LVS clean, have not run DRC yet. Attached (i) LVS out text file (detects more diodes in layout than in schematic), (ii) schematic (iii) subcell schematic (iv) layout images
Note 1: I have used inherited connections to change the "vdd3o", "vdd3r", "gnd3o" and "gnd3r" to find "vd" and "vs" in the bondpad subcell.
Note 2: I tried adding PD_C vias, but I am not sure if I am doing that correctly.
View attachment lvs_output.txt