Assistance with Switched-Capacitor Common-Mode Feedback (SC-CMFB) Circuit Issue

[Serino]

Hi everyone,

I’m currently working on implementing a Switched-Capacitor Common-Mode Feedback (SC-CMFB) circuit based on the topology described in the paper “Analysis of Switched-Capacitor Common-Mode Feedback Circuit” by Ojas Choksi and L. Richard Carley (Pic1). I’ve encountered some issues during my simulations and would appreciate any insights or guidance you can offer.
My circuit is a Fully Differential Folded Cascode Opamp with a Gain of 48dB and a GBW of approximately 2 GHz (before add SC - CMFB block). After adding SC - CMFB block, running PAC, PSTB simulations, and PSS, with an iprobe placed at the SC-CMFB output, the results show that the gain from PAC is consistently below 0 dB, and the loop gain in PSTB is also very low (Pic2). I’ve attached the simulation plots for reference.

Here are some specific details from my testbench setup:

• Clock frequency: 1 MHz
• tsab: 50 µs
• Cload: 100 fF
• C1 (on Vref and Vbias side): 25 fF
• C2 (on Vo and Vb side): 100 fF
• Vref: 900 mV

However, when I ran the transient to check the output common-mode voltage, and the results showed that the Vo value approached approximately Vref, which is as expected. (Pic3).

I’ve also attached the non-overlapping clock waveforms used for controlling the transmission-gate switches (phi1/phi1b on the Vref side and phi2/phi2b on the Vo side). (Pic4)

Despite experimenting with different parameter combinations (cap values, clock frequency, and so on), the PAC/PSTB results have not yet aligned with my expectations.
Additionally, I’m still trying to fully grasp the relationships between the capacitor sizing, Ron, and clock frequency. The paper by Ojas also mentions that the CMFB loop bandwidth should be greater than or equal to the DM bandwidth, but I’m unclear on how to simulate these two parameters. Specifically, I have the following questions:

1. Is the DM bandwidth taken from the Bode plot of the op-amp circuit without the SC-CMFB circuit? (So the Gain DM = 48dB, The unity gain bandwidth roughly 2Ghz as i said?)
2. How can I measure the CMFB loop bandwidth? Is it the bandwidth of the loop gain?

If anyone has encountered similar issues or has suggestions for further reading or approaches that could help me resolve this problem, I would greatly appreciate your insights. Also, if you know any additional resources or papers related to this topic, please feel free to recommend them.
Thank you for your time and assistance.

 

[BradtheRad]

I tried simulations with switched capacitors. I find resistors need to be installed somewhere neighboring the capacitors. Possibly as input resistance. The aim is to create a sensible RC time constant, because switched capacitors by themselves tend to produce unpredictably spikey waveforms.

My schematic is merely a basic experiment yet it takes a lot of adjustments to find capacitor values that influence the incoming frequency in the proper manner.