assignment comparison in verilog

eda_student · Jul 5, 2023

Hi,

what is difference between following 2 assignments?

Code:

always @(*)
    begin
     out_data = in_data;
     end

Code:

assign out_data = in_data;

ThisIsNotSam · Jul 5, 2023

the physical hardware generated by both statements will be the same.

there is only one verilog conceptual difference that the assigned inside the always block can only be done to a *reg* datatype. the assignment using the assign keyword can only be done to a *wire* datatype.

dave_59 · Jul 8, 2023

Synthesis treats the the two construct the same here. But one significant simulation difference is the always @* waits for a change on the RHS first before executing the assignment. If the RHS is a constant, it won't work.

The continuous assign statement executes once at time 0. The SystemVerilog always_comb statement does that too.

assignment comparison in verilog

eda_student

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ThisIsNotSam

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dave_59

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assignment comparison in verilog

eda_student

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