sheikh
Advanced Member level 4
Hello Dears
How can I use fix values and coefficients in vhdl? Does these fix values synthesisable? For instance in equation "Y= 23X" , Is it enough to write :
I did it in my code and the simulation result was ok, But in RTL schematic the port that related to this value eliminated from multiplier and Ise shows this warning:
"Signal <a> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000010111.
Is it a problem for real implementation? ( I mean on FPGA)
Also, it happen when I put some fix values at the input of MUXes.
Regards
mostafa
How can I use fix values and coefficients in vhdl? Does these fix values synthesisable? For instance in equation "Y= 23X" , Is it enough to write :
Code:
Signal a :STD_LOGIC_VECTOR := (0=>'1', 1=>'1', 2=>'1', 4=>'1', others=>'0');
......
y<= a*X;I did it in my code and the simulation result was ok, But in RTL schematic the port that related to this value eliminated from multiplier and Ise shows this warning:
"Signal <a> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000010111.
Is it a problem for real implementation? ( I mean on FPGA)
Also, it happen when I put some fix values at the input of MUXes.
Regards
mostafa