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Ask for Stratrix II I/O Assignment

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arm_learner

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Can I configure 2 difference I/O standard in one bank?

Thanks
 

Yes, u can. firstly, if the 2 i/o standard use same vccio voltage, they can exsit in same bank. secondly, some input buffer and some differential tandards can be in one bank even if they have different VCCIO.
In short, if your assignment can pass 'I/O assignment analysis', you can configure it.
 

ifarmer said:
Yes, u can. firstly, if the 2 i/o standard use same vccio voltage, they can exsit in same bank. secondly, some input buffer and some differential tandards can be in one bank even if they have different VCCIO.
In short, if your assignment can pass 'I/O assignment analysis', you can configure it.

Therefore, if I want to configure SSTL_18 and 3.3V in one bank, just let quartus II to make the consideration. Right?
 

In order to determine where to place I/O you need to take into consideration the VCCIO voltage and also the drive currents of the outputs on adjacent pins..... Trust me, Unless you have a real good reason for wanting to hand pick the pins you would do better to let the tool pick them.
I had to hand pick mine due to limitations with rying to route to the inner balls on the 1mm BGA... After sorting the I/O out to satisfy the VCCIO requirements I then had a somewhat trial and error process so as not to exceed I/O max current requirements from neighborhoods of pins.

Saker
 

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