Ask for help about multi-phase clock generation?

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Davidy

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cmos digital multiphase clock -patent

I want to generate a multi-phase clock for swithed-capacitor circuit such as the figure below. The clock freq. is about 100kHz and the delay between phases is about several handred ns.

Can any one give me some advice?

 

You can reference these papers, but limited information~

A Low Power 1.8V 4-Bit 400-MHz Flash ADC in0.18μ Digital CMOS

AN IMPROVED PHASE CLOCK GENERATOR FOR INTERLEAVED AND DOUBLE-SAMPLED SWITCHED-CAPACITOR CIRCUITS

A 14-b 20-MSamples/s CMOS Pipelined ADC


A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8V power supply

Also interested in the design technique of adc, mistdark@uestc.edu.cn.
 

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    Davidy

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