ask for help about cascading of pipelined adc

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lhlbluesky

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i'm designing a pipelined adc(10 bit 1.5bit per stage),but i find a very strange problem,i designed the first stage and the second stage respectively,and each stage works well;but when i connect the two stages together,the first stage can work,but the second stage doesn't work very well;the output of the sub-adc of the second stage is always 01 in the full range,confused,why?
i estimated the load of the remaining stages,and connected it as the load of the first two stages;and i checked my signal and timing,there is no problem;
but what's the reason?
can anyone give me some advice.
pls help me.
thanks all for reply.
 

can anyone help me?
my comp is dynamic latched structure(in allen's book);
when i simulate the first and secong stage,i use VDC source,but when cascading,the input of the secong stage is the output of the first stage(full differential),and
it has a process of setting,not like the VDC source;but why doesn't it work?
is it the problem of my comp?when i simulate it separately,it works well.
pls give me some advice.
 

Do you use non oversampling clock. Can you draw timing diagram?
 

non-overlapping clok may be problem. show clok phases.
 

you'd better make your question clear first, show timing figure or someting else.
 

this is the timing figure,phi1 is the sample phase,phi2 is the hold phase(for first stage),phi1d is the clock of reset(for down-plate sampling);
i make the sub-adc (two comps) operate in clock of phi1(the sample phase of curent stage),is that right?
or any other improved clock?
 

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