ask for ADHL or verilogA code to model gated oscillator

[beabroad]

i want to model a gated voltage controlled oscillator.
that is to say, there is two inputs, one is Vgate and the other is Vfreq.
when Vgate is ONE, the VCO stops.
when Vgate is ZERO, the VCO start to oscillate, and its initial phase is zero.
i am a new comer to the verilog AMS language, and use Cadence IC design platform to run the simulation.
thank you for your help.

 

[eng_Semi]

analog begin
@(cross( V(Vgate) - vth, +1 ))
x = 0;
@(cross( V(Vgate) - vth, -1 ))
x = 1;

freq = fo + Ko * Vc;
phase = idt(2 * 'M_PI * freq);
V(out) <+ sin(phase) * x;
end

I hope that this code may help u