Dark_Alfred
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Hi,
I have a question about the ASIC Design-Flow and the Tools that are used.
I just watched youtube "FPGA vs ASIC Design Flow" from Xilinx and in That video, he has a Slide which shows the ASIC Design Flow.
My question is:
What Tools are used to do:
- Post-Synthesis Static Timing analysis
- Post-Synthesis Equivalency Checking
- Post Place and Route Static Timing analysis (same tools as for the first Timing analysis ?)
- Post Place and Route Timing Simulation
- Post Place and Route Verification of (Deep Sub-Micron) 2nd and 3rd order effect
?
Thanks for your answers
I have a question about the ASIC Design-Flow and the Tools that are used.
I just watched youtube "FPGA vs ASIC Design Flow" from Xilinx and in That video, he has a Slide which shows the ASIC Design Flow.
My question is:
What Tools are used to do:
- Post-Synthesis Static Timing analysis
- Post-Synthesis Equivalency Checking
- Post Place and Route Static Timing analysis (same tools as for the first Timing analysis ?)
- Post Place and Route Timing Simulation
- Post Place and Route Verification of (Deep Sub-Micron) 2nd and 3rd order effect
?
Thanks for your answers