ASIC Post synthesis simulation in VHDL

kodar · Jan 6, 2014

Hello everyone,

I'm new in the digital world. I'm looking how I can generate a VHDL file representing the cells of the PDK library.

In brief, I've a RTL/VHDL code I synthesis with LeonardoSpectrum. I want now to perform a post-synthesis simulation and put back the synthesized VHDL in the simulator. But the cells of the PDK aren't described in the file and the simulation cannot be performed.

What is the correct way to make this kind of post synthesis simulation? Can the VHDL representation of the cells be generated from the .lib files of the PDK (Liberty format)?

Thanks in advance for your help!

kodar · Jan 7, 2014

I found the solution. In LeonardoSpectrum one have to use the -downto parameter for the write command like this:

Code:

write -format VHDL -downto PRIMITIVES output.vhd

This will write the technology cells along with the synthesized code for post RTL simulation.

ASIC Post synthesis simulation in VHDL

kodar

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kodar

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ASIC Post synthesis simulation in VHDL

kodar

Junior Member level 1

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