ASIC Design for beginner

[brunokasimin]

design asic beginner

hallo,

i'm beginning my project of chip layout design(full custom asic).the vhdl codes were already functionally verified and what i need now is to start the chip design with vhdl codes as my design entry.can someone explain me the common flow step by step from vhdl codes until chip layout??

thx in advanced

bruno

 

[carv_13]

asic design cts synthesis rtl simulation

1) Synthesize your RTL into a netlist using a synthesization tool like design compiler.
2) If you are looking at doing dft, you can perform the DFT at this point of time.
3) Import the scan inserted netlist into the place and route tool you are using along with the relevant timing libraries and timing constraint files.

This is just the overview involved in the process. Take a look into your tool guides to go ahead with each step.

-Aravind

 

[ljxpjpjljx]

common flow: RTL coding-> RTL simulation->synthesis-> DFT inserting-> formal check (RTL to post scan netlist) ->p & r ->CTS-> STA->Post simulation->formal check(post scan netlist to post layout netlist)->DRC LVS->tapeout

 

[jimaaa0]

I think if you take care of power consumption,the power compiling should be insert between synthesis and P&R.