asic design flow simulation problem

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gandhipathik

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hello..

what is the difference between pre-layout simulation and post-layout simulation/?? suppose i have a code of full adder and i want to simulate this code with both pre-layout simulation and post-layout simulation..Then how it performs??
 

gandhipathik said:
hello..

what is the difference between pre-layout simulation and post-layout simulation/?? suppose i have a code of full adder and i want to simulate this code with both pre-layout simulation and post-layout simulation..Then how it performs??
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hi gandhiptik
pre - layout simulation means after synthesis, verifying your gate level net list whether it is functionally working correct or not..where as post - layout simulation means checking your layout for functionality meeting..refer the following link once
https://www.edaboard.com/threads/143081/
 

You can do both simulations in Xilinx ISE. Which means you can do RTL simulation, post mapping simulation and post Place and route simulation in xilinx ise.
 

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