ASIC design flow and info about types of optimization in Verilog

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dhaval parikh

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[hello friends
i wants full ASIC design flow and information about the different types of Optimization in verilog synthesis.]
 

Re: ASIC Design flow

dhaval go throught this link. it is in this thread only.

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Re: ASIC Design flow

Hey Dhaval u just read Smith book for ASIC design flow and read help manuals of cadence
use this link
**broken link removed**
 

Re: ASIC Design flow

u can refer any vlsi book....most of them give the flow...ya smith wil be pretty helpful
 

Re: ASIC Design flow

Hello dhaval,
ASIC flow .....

specification---->behavioural description---->simulation---->synthesis--->gate level netlist is obtained--->flooorplanning (includes power planning)--->placement--->trail route--->rc extraction--->delay calculation--->timing analysis--->clock tree synthesis--->timing optimization(with propagated clock)--->detailed routing--->power analysis--->DRC/LVS--->gds2.

During synthesis optimization can be done for area or timing.By default tool does optimization for area.
 

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