ASIC Code to FPGA Code Conversion

[tut]

Hi All,

What are optimizations, one can do while converting a code written for ASIC into a FPGA one?
Apart from instantiating FPGA specific macros, are there other things needed to be taken care of?

tut..

 

[srilu]

I remember there are some good application notes on ASIC to FPGA conversion coding guide lines in www.xilinx.com
Searching this website may be useful.

-Srilu

 

[eeeraghu]

are timing constrains needed to change while going from asic to fpga

 

[tut]

are timing constrains needed to change while going from asic to fpga

Well not exactly..but can be modified a bit in an absolute need..

 

[tut]

My design is a small IP, for which i have to obtain maximum timing performance(Global Clock Constraint) in XILINX FPGAs.
I have tried increasing the effort level of Synthesis and PAR tools.. but could not acheive the performance..
Is modification of the code is the only option left??


tut..


P.S: MPPR looks as a good option.. :idea: giving it a shot..will post results..

 

[Sparc]

Try using RLOC attributes on Xilinx FPGAs.

 

[Sparc]

I just came across this pdf from the repository. This is for prototyping ASICs with FPGAs. Hope 2 help.

 

[bismillah]

Hi,
Ur design is to be mapped into Fpga, hence u may have to modify the RTL Code.

 

[buzkiller]

Just use Synplicity Certify with the original ASIC code (except for memories and other IP that need to be redone in Coregen)

 

[chaitu2k]

try to identfy all multicycle and false paths in ur design....relax the constraints for these.....if possible also try using the xplorer perl script from xilinx....

 

[FLEXcertifydll]

U should note your rapid prototype's target, it's for source code verification, module emulater , functional test or system estimated.
If you just target the first one, U should not change the source code. But just replace the ASIC special IP, such as PLL or Analog part. Another, you should regenerate the memory EDN netlist for FPGA version. But the control logic of memory as the same.
One important thing, FPGA can't run speed as ASIC. Some times U should use low speed clock.
Another, U should care how many clock domain in your design, and constraint them carefully, if you want a excellent design.
Xilinx device limit: too few BufG

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