ASIC CMOS opamp
Hi guyz,
The following is my design problem.
Need to design a CMOS opamp in the TSMC 0.35um process. Supply voltage is 3.3V
Some of the design considerations are as follows:
1. The opamp will be set-up in the non-inverting configuration.
2. high open loop gain >80dB
3. high unity gain bandwidth requirement > 300MHz
4. needs to have a sufficient closed loop gain
5. output voltage level needs to be at 0V.
Have started the design assuming a 2-pole amplifier. Thinking of a design with 2 stage with miller cap and nulling resistor. This provides high gain but not sufficient bandwidth. What techniques can be used in this config?
Any inputs is greatly appreciated!
thanks!