[SOLVED] array type can't be unconstained

[nsgil85]

Hello,

I have this package code:

---

Code VHDL - [expand]
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package package_arrays is
 
type array_uns  is array ( natural range <> ) of unsigned ; 
 
end package package_arrays ;
 
package body package_arrays is
end package body package_arrays ;

---

and this code:

---

Code VHDL - [expand]
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library work ;
    use work.package_arrays.all ;
    
entity s_disp is 
 
    generic
    ( 
        GENERIC_POS_CONF_ROWS           : positive := 4 ;           
        GENERIC_POS_CONF_DATA_WIDTH     : positive := 8 ;                                   
    ) ;                                             
                                                
    port                                                                                    
    (       
 
        PORT_IN_UNS_ARRAY_DATA      : in array_uns(0 to GENERIC_POS_CONF_ROWS -1)(GENERIC_POS_CONF_DATA_WIDTH -1 downto 0) ;    
 
        PORT_OUT_UNS_DATA           : out unsigned( GENERIC_POS_CONF_DATA_WIDTH -1 downto 0) ;                                                                                                                                                          
        G_RST                       : in std_logic ;
        G_CLK                       : in std_logic      
    ) ;  
    
end entity s_disp;
architecture rtl_s_disp of s_disp is 
 
begin
 
end architecture rtl_s_disp;

---

and i get from Quartus this message :
Error (10294): VHDL Type Declaration error at package_arrays.vhd(52): element type for array type cannot be unconstrained


why do i get this message? i wrote the range in the entity level

Thanks
Gil

 

[FvM]

Unconstrained array element types are basically supported by VHDL-2008, not before.

As far as I understand, a separate type declaration for the unconstraint unsigned element would be needed, means the shown syntax won't be right in VHDL-2008.

The other question is if your tool supports this VHDL-2008 feature.

 

[nsgil85]

So how would you suggest to declare this unconstrained array?

Quartus support VHDL-2008 and meanwhile i manged to synthesis it , but this should be implemented on ISE.

Thanks
Gil

 

[TrickyDicky]

The syntax you have is correct - the type assignment is done at the object declaration.
ISE doesnt support VHDL 2008. So you'll have to constrain the array at the type declaration.
Only Vivado 2014.4 and later has 2008 support.