array as an output of a VHDL function

Similar threads

• VHDL array clearing overflow memory

  • Started by KfirMaymon84
  • Jun 14, 2024
  • Replies: 7

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  [SOLVED] Delaying the output by 2 clock cycles in FSM in VHDL

  • Started by metamisers
  • Aug 2, 2024
  • Replies: 3

  PLD, SPLD, GAL, CPLD, FPGA Design
• G

  VHDL abs() function speed

  • Started by gahelton
  • Nov 17, 2023
  • Replies: 4

  PLD, SPLD, GAL, CPLD, FPGA Design
• X

  VHDL Testbench (Weird output in the simulation)

  • Started by Xenon02
  • Jan 21, 2024
  • Replies: 18

  PLD, SPLD, GAL, CPLD, FPGA Design
• A

  VHDL code to that make text on lcd

  • Started by aiman89
  • Nov 15, 2024
  • Replies: 9

  PLD, SPLD, GAL, CPLD, FPGA Design