Array Antenna Amplitude Tapering for SLL Reduction

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farzanehjun

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Hi every one
I designe waveguide slotted array with -27.5 dB SLL in CST,
when I fabricate and test it
SLL increase to -25 dB
Have any one information about space tapering or other methods to reduce SLL in simulation?
 

it may be because of your fabrication tolerance.
 

I think 2-3dB defradation of sidelobe is due to fabrication. In my experience of an array of 16 horns with a 30dB SLL goal, I had 2 dB degradation due to feeding network and cables and 1 dB due to antenna itself mechanical errors that finally concluded to a 27dB SLL. Specially in slot which error factors including the angles of slots, amount of loss of waveguide, position of slots,... affects SLL.
 

Something magic . Typically for complicated Hi gain antenna that is around -15 dB. But in your case should something simple, sectoral, equivalent to some dipole area.
Can you drop your project?
 


Thanks for your reply
I know thatthe fabrication process is major problem, as you said.
But , you know, I can not improve fabrication and so I have to design Antenna with better SLL
Do you any idea about reduction SLL in simulation? for example less than -30 dB?

- - - Updated - - -

Bob60 said:
Something magic . Typically for complicated Hi gain antenna that is around -15 dB. But in your case should something simple, sectoral, equivalent to some dipole area.
Can you drop your project?
Click to expand...

So sorry, I can't drop it.
 

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