pokemonstation
Junior Member level 1
cadence pvs
Hi all,
I have several questions regarding ARM libraries, IBM PDK, and Cadence PVS.
ARM Libraries
1. Has anyone used it before? Does it have layout view for Cadence Virtuoso tool
IBK PDK
1. After I installed it, I got the following warning message in Virtuoso CIW
2. Another warning message I saw in Virtuoso is as followed
3. For those that have used IBM 45nm 12SOI PDK, I have a specific question on the nmos/pmos cell. I am really confused because in both cells, there are two "poly-like" instances that are parallel (and have the same length) with the gate poly and they are above/below drain/source of the transistor. Does anyone know what that is?
Cadence PVS
1. Is Cadence QRC included as part of Cadence PVS?
2. I think I have access to PVS70 and PVS80, can anyone tell me what's the difference between them?
Thanks in advanced!
Michael
Hi all,
I have several questions regarding ARM libraries, IBM PDK, and Cadence PVS.
ARM Libraries
1. Has anyone used it before? Does it have layout view for Cadence Virtuoso tool
IBK PDK
1. After I installed it, I got the following warning message in Virtuoso CIW
This is just the first 4 lines of the 50-60 lines warning message. I think this has something to do with the bindkey file (ibmPdkBindkeys.il). Does anyone know how to fix this problem?*WARNING* Modifier Meta is unassigned, illegal or disabled.
*WARNING* Invalid bindkey key string: Meta<Key>Insert
*WARNING* Modifier Meta is unassigned, illegal or disabled.
*WARNING* Invalid bindkey key string: Meta<Key>Insert
2. Another warning message I saw in Virtuoso is as followed
This warning message appears after the SKILL file ibmPdkMenu.def is loaded. I wasn't able to locate the cause of this problem. Can anyone help?\w *WARNING* No user triggers registered for viewType schematic.
\w *WARNING* No user triggers registered for viewType schematicSymbol.
3. For those that have used IBM 45nm 12SOI PDK, I have a specific question on the nmos/pmos cell. I am really confused because in both cells, there are two "poly-like" instances that are parallel (and have the same length) with the gate poly and they are above/below drain/source of the transistor. Does anyone know what that is?
Cadence PVS
1. Is Cadence QRC included as part of Cadence PVS?
2. I think I have access to PVS70 and PVS80, can anyone tell me what's the difference between them?
Thanks in advanced!
Michael