Area report: ASIC Design

[subhash_chevella]

hello all,

First, I synthesize the desing using 90nm technology.
After, suppose if I changed the library to 65nm technology by keeping the same constraint file and also the same clock.

Can any one explain what are the changes that will occur in terms of Area in both the cases and why?

thanks & regards,
Subhash

 

[Syswip]

Hi Subhash,

Usually your frequency should be increased and area should be decreased for 65 nm. But it also depends which kind of library you use. For example if you use low power 65 nm technology your frequency may go down in this case.

Bests,
Tiksan

 

[subhash_chevella]

Hi Tiksan,

Ya I agree with you.

But, Suppose If I didn't change any thing except Library (from 90nm to 65nm) what will happen?
I tried this. In the report I am getting less cell count in 65nm compared to 90nm. Why is it so?

thanks and regards,
Subhash

 

[oratie]

Because you keep the same clock, as 65 cells are faster, than in 90, you need less cells (for example buffers) to reach the same frequency.

 

[Syswip]

Can be nothing strange. You changed the library and the tool synthesized in different way.
It is OK do not worry.

 

[subhash_chevella]

I agree that 65nm cells are faster compared to 90nm.
So, when I am changing the library (from 90nm to 65nm), timing related parameters should change.
and the logic implemented in both the cases is same, right? So, how the cell count will be differ?

 

[sam33r]

Because you keep the same clock, as 65 cells are faster, than in 90, you need less cells (for example buffers) to reach the same frequency.

IMO this is not true.
Try keeping the same library say 45nm. Increase the the frequency you will notice the area going up, Because there is a trade off between frequency and area. I am not sure why this happens but it does. Can anyone add to the explanation?

 

[wsong0210]

Some facts which may help you understand it.
1. The same logic or function can be implemented by different cells, For example, ~(A+B) can be implemented as a 2-input NOR; or 2-input OR plus INV; or 2 INVs plus a 2-input AND. These combinations are the same, but have different cell counts.
2. The driving strength of cells can be different and this will affect the area. For example the 4x INV is larger than 2x INV
3. To reach the timing constraints, the synthesis tools can duplicate some cells to reduce the fan-out counts of each cell, which would make the circuit faster.


Back the original question:
Usually the same cell in 65nm lib is faster and smaller in 90nm.
First we assume the netlist is exactly the same in 65nm implementation as in 90nm.
The area of the 65nm is smaller as every cell is smaller.
Now we can think about the clock period. As the 90nm implementation already meets the constraint, so the clock period in 65nm is smaller than constraint (obviously).
The synthsis tool will always try to use less area to meet the constraints. Therefore, the result netlist in 65nm will be different, because the synthsis tool tries to use even less area to just meet the timing constraints. (here may confuse you.)

For an example:
Assuming in 90nm, your circuit run to 100MHz, area about 1000um^2
in 65nm, if the netlist keeps the same, the frequence can be around 120MHz, and area is about 600um^2
As the synthesis tool tries to reduce area while keeping satisfy the timing constraints,
Finally you may get a different circuits of 100MHz with area 400um^2

 

[subhash_chevella]

hi wsong0210,

thanks a lot..

regards,
Subhash

 

[pavanks]

Hi i just want to mention one more imp thing here that is Hold.
You will see more hold violations here as ur min path might be violated.
But the tool will automatically add buffers to meet the hold requirement here.

But still u can say the overall area would be decreased in 65nm(coz of the small size cells and easy to meet setup timing).

But at the backend u will have more DRC's to fix and also more crosstalk to fix.