Area-aware Logic Synthesis
- Thread starter ivlsi
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oratie
Full Member level 6
It performs some kind of placement (DC-topo makes not-legalized placement), calculates distance between cells (and wire length) and use TLUplus file for calculating RC values. The main difference between WLM and Topographical is that in WLM mode it use esimated wire length (some average value), in Topo mode it use more or less real wire length based on cell placement.
ivlsi
Advanced Member level 3
Thanks oratie! But, where is the TLUplus file taken from? from floorplaning? But how the floorplaning might be performed without any info from the Logic Synopsys about the cells area. Somehow this circuit should be broken :smile:
oratie
Full Member level 6
TLUplus come with foundry tech files (or you may generate them from ITF or GRD tech files).
The floorplan may comes from different sources:
1. You have previous design, so you may use it as reference (scale somehow or manually modify)
2. You did (at first) non-topographical synthesis (with WLM, as example), estimate the cell area, take inot account desired utilization (in order to not have any routing congestion issue in the future) and create floorplan.
3. The full chip layout owner gives floorplan of your block (based on full-chip requirements)
It is iterative process.
The floorplan may comes from different sources:
1. You have previous design, so you may use it as reference (scale somehow or manually modify)
2. You did (at first) non-topographical synthesis (with WLM, as example), estimate the cell area, take inot account desired utilization (in order to not have any routing congestion issue in the future) and create floorplan.
3. The full chip layout owner gives floorplan of your block (based on full-chip requirements)
It is iterative process.
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