Are Virtex 2 Pro I/Os designed to comply with 2.5V LVPECL?

Similar threads

• A

  Map report remove most coregen blocks and designed this as Loadless

  • Started by antonkurka
  • Aug 24, 2024
  • Replies: 7

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  [SOLVED] Delaying the output by 2 clock cycles in FSM in VHDL

  • Started by metamisers
  • Aug 2, 2024
  • Replies: 3

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  [SOLVED] Virtex II Pro doesn't work properly

  • Started by MSAKARIM
  • Nov 4, 2022
  • Replies: 10

  PLD, SPLD, GAL, CPLD, FPGA Design
• O

  Issues with ALTERA EP600

  • Started by OiramCisulix
  • Oct 18, 2024
  • Replies: 13

  PLD, SPLD, GAL, CPLD, FPGA Design
• M

  Problem with PS/2 communication over UART

  • Started by mtaciano
  • Jul 7, 2023
  • Replies: 5

  PLD, SPLD, GAL, CPLD, FPGA Design