are there problems in this layout?

[renwl]

metal 4
|
via3
|
metal3
|
via2
|
metal 2
|
via1
|
metal1
|
contact
|
poly2
poly1

I want to draw a line on metal 4 from the double poly capacitor. are there any problems when there are so many vias up the poly? is it reliable on process?

 

[eeliuliu]

it may increase the series resistance and parasitic cap. if your working frequency isn't very high, I think it's ok!

 

[renwl]

the frequecny is low frequency circuit.
because the vias need heat process and CMP,the more vias mean more process steps up the poly. I want to know, is it affect the reliablity?
thanks

 

[pyth2004]

hi,

The process you used has chemical mechanical polishing? if no, the surface of upper metal layers will not be flat especially on the top of the double poly cap. It will cause over etching of metal wires over the edging of the poly cap and would cut it.

metal 4
|
via3
|
metal3
|
via2
|
metal 2
|
via1
|
metal1
|
contact
|
poly2
poly1

I want to draw a line on metal 4 from the double poly capacitor. are there any problems when there are so many vias up the poly? is it reliable on process?

 

[renwl]

I also dont know the process use the CMP or not.
how can I know it?
I think it's a standard process step,right?

 

[williamy]

now in standard VLSI process, the CMP is often used. Moreover, you can evenly layout the vias