Are there any ways to make the PM, GAIN, higher and ICMR- lower?

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lu091234

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Here's the netlist of this CMOS OP Amp schematics.

Code: 
M_M1 N16151 VIN N16182 N16182 MbreakN L=0.1u W=9.5u
M_M2 N16178 VIP N16182 N16182 MbreakN L=0.1u W=9.5u
M_M3 N16151 N16151 VDD VDD MbreakP L=0.1u W=5u
M_M4 N16178 N16151 VDD VDD MbreakP L=0.1u W=5u
M_M5 N16182 N16219 VSS VSS MbreakN L=.95u W=19u
M_M6 VO N16178 VDD VDD MbreakP L=1.3u W=76.1u
M_M7 VO N16219 VSS VSS MbreakN L=1.3u W=76.1u
M_M8 N16219 N16219 VSS VSS MbreakN L=.95u W=19u
R_R1 N16219 VDD 45k TC=0,0
And it's based on .38 TSMC CMOS

I have problem increasing the Gain and IMCR- Are there any ways to reach that without increasing lots of the area of it?
 

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FvM said:
What's the achieved figure, what's your target?
Click to expand...

Here's the statistics of this circuit, and my Goal is to make Gain becomes over 700 and ICMR- becomes -1.5

Gain = 97.094 V/V
GBW = 20.43 MHz
SR+ = 37.1524 V/us
SR- = -19.6375 V/us
ICMR+ = 1.55 V
ICMR- = -0.65 V
PM = 75.3947 degree
BW = 210.401 kHz
Total Area = 1559.34644400786 um^2
Click to expand...
 
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lu091234 said:
Here's the statistics of this circuit, and my Goal is to make Gain becomes over 700 and ICMR- becomes -1.5
Click to expand...
Breifly,

1) Phase Margin. Increase. This type of architecture usually has a miller pole splitting capacitor between the two stages. Without it the dominant and non-dominant poles become close and give bad phase margin. Look up miller two stage OTA or Op Amp and using miller compensation cap to push out non dom pole beyond gbw.
2) ICMR- If you want -1.5V that only leaves 150mv for the input VGS and lower Ibias device. Doubtful you will get saturation with that. But, you haven't shown vt of this process either.
3) Higher gain without drastically larger devices. That gain seems achievable with this architecture.
If you want a high ICMR, that usually requires making deltav very small and much larger W devices. That and vt in this case needs to be very small.
 
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Sounds like you want a complex op amp's performance
from one of the simplest topologies. Not likely.

Without changing topology, about the only idea I have for
increasing negative input common mode range it to see if
your process offers a "native" / "zero-VT" FET. Some do,
some (esp. low cost digital-only) don't. A rail-rail input
topology would roughly double the area involved.

If you want phase margin, run it hotter. But that steals
from DC gain (decreasing Rout). Adding a second
differential gain stage can help small signal AVOL & BW
a lot but you don't want to increase area.

Have you even tried to play with simple optimization,
"stimulus, response" style, device (pair) by device (pair)
seeing what benefits and ehat costs you, these interests?
 
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Would a longer channel length increase the gain by reducing channel length modulation and increasing the MOSFET output resistance?
Or is that offset by a reduction in Gm?
 

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Yes, and I seemed to make all the parameters the best, there's an auto judge system, and I tried to make the total score higher
 

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