Are the pins of an FPGA protected?

Hello everyone.

I am working on the Xilinx Spartan3 FGPA. I have a very simple query.

The pins of the FPGA can be configured as an input or output. Consider the scenario

that:

1. Pin is configured as output of logic 0. And I happen to accidentally give an input

of logic 1.

2. Pin is configured as output of logic 10. And I happen to accidentally give an input

of logic 0.

In any of the above mentioned cases, will there be a current surge from Vcc to GND? Are

the pins of the FPGA protected from these sorts of accidents? Can it permanently damage

the pin and/or FPGA?

Kindly let me know your opinions.


Thanks and Regards,
John

Hello John;

yes there is a keeper circuit but it is mainly intended to protect from ESD. And yes The pin can be permanently damaged in the scenarios you mentioned. Moreover, the scenarios you mentioned are ones of the most famous reasons to burn out the whole spartan3 chip.

regards,

Hi Sameh,

Thanks for the initiative. It means that the FPGA needs protection form these situations. Is it possible to have some kind of external circuitry which can protect the FPGA? I dont mind the fanout or the operating speed reducing by some amount. My main concern is that the FPGA should not burn out.

Please let me know your opinions.


Thanks and Regards,
John

Series resistors at the pins are the most effective means against damaging the FPGA by overcurrents due to output shorts. They are provided
for external IOs on some development kits, reducing of course the available static output current and signal speed.

Hi FvM,

Thanks a lot for your help.

Regards,
John

sameh_yassin99 said:

Hello John;

yes there is a keeper circuit but it is mainly intended to protect from ESD.

regards,

Click to expand...

I believe keeper circuit is not to protect the the device from ESD. It is there to drive a tristate weakly to last value when no driver is present.
There are two clamping diodes are present at each to protect from ESD to some extent.
Series resistor is a good external measure.

for better understanding refer to device datasheet.

Hello John_Correa & Kvingle,

I double checked to review the function of a keeper circuit and it was as follows for spartan family:

"Each I/O has an optional keeper circuit that keeps bus lines from floating when not being actively driven. The KEEPER circuit retains the last logic level on a line after all drivers have been turned off."
so thanks kvingle for correction.


Again to the main topic, How to protect our FPGA ? for me I had a tough experience in this issue on my custom PCB. I suffered from 3 or 4 FPGA burnouts! and the solution can be summarized as follows:

1- Pay a great attention for the common ground between all chips on the same PCB. Also pay a great attention for common ground between all cards. Usually the system contains a back-plane or motherboard, this back-plane must have a ground plane at one of its layers.

2- The power supply ripples is an evil. Be extremely sure that your power supply doesn't have a bad transient response. You can measure this using an oscilloscope.

3- use the internal pull-up and pull-down resistors that are located at the IOB of the FPGA, they can easily be programmed from ISE instead of soldering external resistors. To use the pull-up and pull-down resistors, you can easily specify that using either the UCF file or graphically from the GUI.
example, to drive the pin clk_out as pull-down from ucf as text file
regards,

Hi Sameh,

Are the internal resistors enabled by default? I had tried measuring the values of internal resistors and both of them turned out to be 15 ohms. I had not explicitly enabled the resistors.

Nevertheless I'll go ahed with the technique you have mentioned and I'll also let you know the outcomes, if any.

If you have any more data on the same, please let me know.


Thanks and Regards,
John

Hello John;

The internal pull-up or pull-down resistors are not enabled by default. Please read www.xilinx.com/support/documentation/data_sheets/ds312.pdf data-sheet, page 11 under the title IOB you'll find alot of useful information.

regards,