Are INL/DNL important for sigma delta ADC or NOT???

[sehun1119]

inl spec

I saw a post on this board that INL/DNL are not important for the sigma-delta ADC.

Is that true?

Why is that? Is it because INL is obtained from a plot of digital output code as a function of its analog input voltage level while the sigma-delta ADC has 1bit (2 levels) digital output bitstream?


I got a SDT toolbox and studied and simulated this tool. Now, I would like to do some circuit level design and simulations in order to determine some non-ideality parameters such as clock jitter, op-amp slew rate, noise and etc.
Could you please give me any good references and/or books for this study?

Thank you in advance,

 

[renwl]

sigma delta adc

I saw a post on this board that INL/DNL are not important for the sigma-delta ADC.

Is that true?

Why is that? Is it because INL is a plot of digital output code as a function of its analog input voltage level while the sigma-delta ADC has 1bit (2 levels) digital output bitstream?


I got a SDT toolbox and studied and simulated this tool. Now, I would like to do some circuit level design and simulations in order to determine some non-ideality parameters such as clock jitter, op-amp slew rate, noise and etc.
Could you please give me any good references and/or books for this study?

Thank you in advance,

INL/DNL are important for the sigma-delta ADC too.

you can read the book <<Delta-Sigma Data Converters - Theory, Design and Simulation>>

 

[mists]

adc dnl

then why many sigma-delta ad/da converter's datasheet don't give DNL/INL spec, especially in audio band.

 

[sehun1119]

dnl 1bit

Thanks for the reference, renwl.

Like mists said, I have not also seen INL/DNL on datasheets of most commercial sigma delta ADCs.

They seem to care SNR, ENOB mostly.

Let's say INL/DNL are important. Then, as I said INL can be obtained from a plot of digital output code VS input analog values, how could we get or calculate INL for sigma delta ADC which has only one bit output (two level digital codes)????

 

[Alan_Nesta]

dnl inl for sigma delta

Because oversampling and if we use 1-bit quantization, we need not take care to INL and DNL;
if we use multi-bit quantization, DAC linearity will affect our SDM's SNR and THD.

 

[bkt22]

sigma delta adc data sheet dnl inl

I saw a post on this board that INL/DNL are not important for the sigma-delta ADC.

Is that true?

Why is that? Is it because INL is obtained from a plot of digital output code as a function of its analog input voltage level while the sigma-delta ADC has 1bit (2 levels) digital output bitstream?


I got a SDT toolbox and studied and simulated this tool. Now, I would like to do some circuit level design and simulations in order to determine some non-ideality parameters such as clock jitter, op-amp slew rate, noise and etc.
Could you please give me any good references and/or books for this study?

Thank you in advance,

In most of Nyquist rate ADC's, there is a one to one correspondence between analog input and digital output code, ie, if an analog sample is given as input to ADC, digital output code is available after a fixed latency of x seconds. The main point to note is that x is deterministic in all Nyquist ADC. The latency may vary between different types of Nyquist ADC's and can be calculated easily.
Here, you can easily define INL/DNL and then interpret it to understand how the ADC is working.

However, the situation is different in oversampled ADC's. Because of oversampling and feedback, we get higher resolution, but input goes through loop filter, comparator and then the digital bit stream goes through decimation filter (downsampling) before the actual digital code is obtained at output. Here, you cannot define a deterministic latency between input analog sample and output digital code. Hence, INL and DNL do not make much sense in a sigma-delta ADC.

However, you can still define INL/DNL for a sigma-delta ADC by using statistics and large number of input samples, but interpreting it is difficult in case of sigma-delta ADC - SNDR, SNR and SFDR provides the necessary performance information.

Hope this explanantion is clear.

Regarding references for circuit design and simulation, the best source would be some M.S or PhD thesis or books from Springer/Kluwer which are adaptations of PhD dissertations.
Depending on switched cap/continuous time sigma delta, there are various options present.

Some free links :

**broken link removed**
**broken link removed**
http://www-cis.stanford.edu/icl/wooley-grp/alois/icl1_1.pdf
http://web.engr.oregonstate.edu/~moon/research/files/Mustafa_Keskin.pdf
http://web.engr.oregonstate.edu/~moon/research/files/Jose_Silva.pdf
http://ir.library.oregonstate.edu/dspace/bitstream/1957/4276/1/dissertation.pdf

 

[sehun1119]

inl dnl from sigma-delta adcs

Thank you, bkt22, so much for very detail and clear explanation.

It helps me a lot.

Appreciate it.