AOCV derates in sta sign off? how intra-die voltage&temp is taken care in AOCV sta?

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priya_thakur

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AOCV derates in sta sign off? how intra-die voltage&temp is taken care in AOCV sta?

Hi All,

I have a basic doubt on AOCV derates..

The AOCV derate is to model the local on chip process variations.
It models systematic variation as a function of distance and random variation as a function of depth.
So the AOCV derates only models the process variation on chip (within chip).

How about on chip voltage and temperature variation? how it is model is AOCV timing sign-off.

Appreciate the feedback.

Thanks,
Priya
 

Re: AOCV derates in sta sign off? how intra-die voltage&temp is taken care in AOCV st

hi Priya...
voltage and temparature they do consider in analysis.
 

Re: AOCV derates in sta sign off? how intra-die voltage&temp is taken care in AOCV st

There are multiple PVT conditions at which the chip has to work so you have to close the timing at each of them.
Vdd1 : 1v , Temp= -25/125v, P=SS/FF/TT : Frequency 100MHz
Vdd2 : 1.2v , Temp = -25/125v , P=SS/FF/TT : Frequency 200Mhz

now P covers the timing at mostly 3sigma corners which is the statistically estimated spice models. Now the process variation has increased so AOCV has been introduced which is modeled around 3sigma corners. AOCV models have statistical variation of the spice models and timing models are generated for each PVT condition. The AOCV models also depend on the depth of the logic. This is used to reduce the overall pessimism in the timing sign off and some companies are doing 1.5sigma for spice models or even TT along with AOCV to reduce the pessimism.
 

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