Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

AOCV - Advanced On Chip Variation

Status
Not open for further replies.

ukint

Member level 2
Member level 2
Joined
Jun 15, 2006
Messages
45
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,597
Hi,
I am looking for some documents in Advanced OCV.
Can anyone help with the same?

Thanks,
Vivek
 

Hi Vivek,

What kind of questions do you have? Disclosure: I work for CLK DA, the company erikl pointed too in the last response to your question.

At its simplest, AOCV is a way to specify a derate factor for the delay through a particular cell during static timing. The AOCV tables can include information so that a different derate value is chosen for a cell at the beginning of a path vs. the same cell near the end of the path. AOCV is very useful for you to start taking variability in to account in your static timing without switching to a full statistical timing methodology.

I posted a few links to Synopsys and Cadence web sites on our company blog. (The forum software won't let me post links here since I'm a new member.)

At this point, many static timing tools handle AOCV in some form.

You can get AOCV tables from your library vendor or you can generate them yourself if you have more specific needs than what the library vendor provides. The most common way to create tables is to use some version of SPICE. As erikl pointed out, CLK DA has a special purpose tool for building tables, too. They are a lot faster and less complicated than using SPICE for creating tables - especially when you are dealing with Monte Carlo simulation and complex cells.

Feel free to get in touch directly if you have more questions or post here. I'll keep an eye on the thread.

Ahran
 
We wrote an article about stage-based OCV (AOCV) that goes in to some detail about how tables work and some of the additional data analysis that can be done with the raw data used in the derate calculations.

**broken link removed**
 

Hi adunsmoor,
I am new to OCv and AOCV concept. From the articles which you pointed, I came to know that OCV is optimistic for shorter paths. How can OCV be optimistic for shorter paths?
As per my understanding in OCV a common derate value is applied to all the clock and data paths. Since we are applying a common value, we are considering the worst case derate. The worse case will not exist for most of the paths and hence the overall result will be pessimistic.
Please correct me, if I am wrong.
 

Simply to say, AOCV use different derating ocv factor for different stage. In traditional ocv, one constant derating factor is applied to whole chip. But, from statistical analysis, on-chip-variation will be counteracted with stage increasing. So, AOCV (stage based ocv) is put to reduce over-design.
 

Attachments

  • Stage_Based_OCV_Overview.PDF
    201.5 KB · Views: 473

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top