Anyone knows how to implement slew rate detect circuit?

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vivimz

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Hi, Is there anyone who has some experience about the slew rate detect circuit? Pls share with me some design idea. Thanks a lot!
 

vivimz said:
Hi, Is there anyone who has some experience about the slew rate detect circuit? Pls share with me some design idea. Thanks a lot!
Click to expand...


Maybe you'll get some ideeas if you could define first for everyone what is the "slew rate" and which is the frequency range and the speed of the DUT (device under test).

thx,
 

you can try the differential operational circuit, and convert the slope to output voltage.
 

hi, the slew rate here is the rising and falling slope of the high speed signal. The signal speed is around 2Gbps. Basically we want to detect the signal rising slope, if the signal rising slope is too slow we want to make it faster.

Thanks for your reply
 

Hi,

Could you ac couple the edge signal and rectify it into a dc level. The sharper the edge (faster slew rate) the higher the ac couple and the more dc level? I don't know how fine a slew rate range your working on but if it is a gross error this could work.



dfullmer
 

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    vivimz

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vivimz said:
hi, the slew rate here is the rising and falling slope of the high speed signal.
Click to expand...

measured between 10% and 90% of the signal amplitude...


vivimz said:
The signal speed is around 2Gbps. Basically we want to detect the signal rising slope, if the signal rising slope is too slow we want to make it faster.

Thanks for your reply
Click to expand...

Let's go slowly. A 2Gbps is not the signal speed but the data speed on the bus.
For a specific combination of data, say 10101010... the signal frequency will be 2GHz.
For other combination of data, the signal frequency could be 1MHz.
So, first of all: the data stream is continuous or not ?
Second: do you have a good oscilloscope on which you may observe the stream shape?

I'm asking because a slew rate could be anywhere between 1V/uS and 13000V/uS
and you know better how looks your signal. There aren't to many options for such a design...
 

Solution:

Couple signal via a small cap (50fF) to a current summing node. If the cap current compensate the bias current also injected into this node the current sum change sign. That is used as digital signal. Two comparators define the 10%/90% transition region. To adapt to this huge slew rate range use different current settings. I think you want to built a an autoconfiguration serial interface?
 


Hi dfullmer, thanks. I am trying to use this way currently.

Added after 8 minutes:


Hi rfsystem, you are right. This is designed for some adaptive equalizer.
I am not sure if i got your point for this current summing solution. Is it a kind of current square difference circuit? Could you kindly share some schematics for reference if you have it?

Thanks a lot !
 

 

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