Anyone know Verilog convert to VHDL ( can help me )

[kun]

convert from Verilog to VHDL
i really need help~~

module dac (DACout, DACin, Clk, Reset);
output DACout;
reg DACout;
input [ 'MSBI :0] DACin;
input Clk;
input Reset;

reg ['MSBI+2:0] DeltaAdder;
reg ['MSBI+2:0] SigmaAdder;
reg ['MSBI+2:0] SigmaLatch;
reg ['MSBI+2:0] DeltaB;

always @(SigmaLatch) DeltaB = {SigmaLatch['MSBI+2], SigmaLatch['MSBI+2]} << ('MSBI+1);
always @(DACin or DeltaB) DelTaAdder = DACin + DEltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge Clk or posedge Reset)
begin
if(Reset)
begin
SigmaLatch <= #1 1'b1 << ('MSBI+1);
DACout <= #1 1'b0;
end
else
begin
SigmaLatch <== #1 SigmaAdder;
DACout <= # SigmaLatch['MSBI+2];
end
end
endmodule

 

[jimjim2k]

Hi

1. Use X-HDL with careful options setting

tnx

 

[kun]

Hi jimjim2k

thankss for reply

but i don have X-HDL

err can you help me please~~

is really important to me please ~~
convert for me

 

[viswanadh]

Try this link
**broken link removed**

or

**broken link removed**

 

[kun]

i registered but after i submit error ...
so i cant enter the web
can you help please

is really a big big problem to me now haiz~~~

 

[viswanadh]

OK. I registered and here is the download link

Windows Executable

http://www3.syncad.com/ftp/v2vinstall.exe

Linux Binary

http://www3.syncad.com/ftp/v2vinstall-linux.tar.gz

This is a demonstration copy.

 

[kun]

thanks ^^
err i try running it
how is it like
all i see is file that i can read

is it a progam thats help to covert or just a few file for me to read ??

 

[viswanadh]

It will convert files containing up to only 500 lines of code.

 

[niko_zhang]

lic?