Anyone has this feeling in LNA design? [About Source DeGen]

Using the famouse single-end casecode source degeneration structure for LNA design, I get this feeling:

1. When using CMOS, the larger source degen inductor, the closer GA and NF circles;

2. While using npn (SiGe), I get the reverse trend.

Anyone has this experience? Please comment.

is there any reason behide?

(1) You have to make sure that the noise performance of your CMOS model is accurate. Most foundry don't guarantee the noise performance.

(2)Have you tried to use inductance below 1nH?

(3)Tune the bias current.

Re: Anyone has this feeling in LNA design? [About Source DeG

dsjomo said:

(1) You have to make sure that the noise performance of your CMOS model is accurate. Most foundry don't guarantee the noise performance.

Click to expand...

You mean:
a. CMOS noise model is less accurate than SiGe?
b. You are suggesting that the source degen will further separate the noise and GA circles just as SiGe does?
I have an IBM application note about their SiGe process noise performance. The author suggest to put a 2nH source degen inductor so that the Sopt (for FNmin) and conj(S11) come very close.

dsjomo said:

(2)Have you tried to use inductance below 1nH?

Click to expand...

No. But what is supposed to happen while using a small inductance?

dsjomo said:

(3)Tune the bias current.

Click to expand...

Not understand.

Re: Anyone has this feeling in LNA design? [About Source DeG

(1) a. Yes, CMOS noise model is less acurrate unless you fit the model according to the measured noise data. Normally, the model engineer only fit the S parameters. On the other hand, a accurate BJT or HBT AC model always gives a acceptable noise performance.

b. First, you have to know why a emitter degenerated HBT has a closer distance between Γopt and Γin*. There is a very classic paper written by the Nortel group, you can find in IEEE library.

Title:A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design
Author:Voinigescu, S.P.; Maliepaard, M.C.; Showell, J.L.; Babcock, G.E.; Marchesan, D.; Schroter, M.; Schvan, P.; Harame, D.L.;
Date:Solid-State Circuits, IEEE Journal of
Volume 32, Issue 9, Sept. 1997 Page(s):1430 - 1439

How close the Γopt and Γin* depends on bias, device size and degen. inductance under one fixed frequency.

(2) The optimum inductance may be less than 1nH.

(3) Because how close the Γopt and Γin* depends on bias, device size and degen. inductance under one fixed frequency, so you have to consider the bias current.