analogic
Junior Member level 1
say for 1MHz sampling rate and 9bit resolution, is it possible to design a comparator with only NMOS? if we consider only regenerative comparator, and dont consider amplifier based comparator.
i m thinking it is impossible, because if NMOS as latch and the load is also NMOS (gate connected to CLK or Vdd), the initial gain will be on the order of gm1/gm2, and the regenerative time will be very long, so not feasible. does anyone has some idea or comment?
Thanks.
i m thinking it is impossible, because if NMOS as latch and the load is also NMOS (gate connected to CLK or Vdd), the initial gain will be on the order of gm1/gm2, and the regenerative time will be very long, so not feasible. does anyone has some idea or comment?
Thanks.