anyone can give me some helps?

[skycanny]

At present , I want to implement error corrcet coding by FPGA. I have learned vrilog HDL for several days and can use it to describe common digital circuits. Meanwhile,I am reqiued to use Xilinx device. I am able to design simple digital circuits by verilog and using ISE and download it to the demo board. However ,I do not know what to do next step. Becase I am new to EDA, especially to Xinlix.if anyone who have error correct coding experience,please help me.Tell me what shall I do next step and what should I pay attention to.

Regards!!!

 

[nand_gates]

Which Xilinx eval board ur using??
1. Write verilog code for ECC module.
2. Write verilog testbench for ECC module.
3. Do simulation and fix the bugs if any in ur ECC code.
4. Syntesize and generate bit file for ur module
5. Download it to FPGA.
6. If ur ECC module is pure combinatorial then you can use the
input switches to apply input to ur module on FPGA board and
use LED on FPGA board to display ur result.

7. If ur ECC code is not combinatorial You can write synthesizable
testbench and Synthesize it with module. In this case you can use
LEDs on FPGA board to indicate test passed or fail!

Hope this helps

 

[skycanny]

Hi,nand_gates,Thank for your replies. And I find that your replies can give me many guides. I am going to try out as the steps you showed to me and if I have trouble on continuing them in the near future,I hope to get support and help from you.

I searched the websites and forums covering the error correct coding on internet, but failed. Could someone knowing this kind of websites and forums show me some links to help me! Thank you in advance!
Happy new year to everybody!!!

 

[hamadeh]

You can find some free ECC core at opencores : **broken link removed**
Check it maybe it will help you ...

 

[soccer]

what you should do is to just verify your design

 

[bibo1978]

Nand_gates had summerized it all but he had missed a vital detail which is to simulate your design post place and route model which is generated with the ISE tools with the Standard delay file "SDF" which is generated with it, this way you can be MORE sure that your design had be synthesized well and can work with the clock speed of your board, then u may start the hardware debugging process, which can be done in various ways, Nand_gates had descriped the easy solution for that,

that's all folks

 

[skycanny]

Firstly thank you,all guys!

Actually, I just have a general understanding abour ecc, so I need some forums and websites discussing ecc in detail. I believe this will give me great help!

Though I have studied the steps given by nand_gates, I am not able to describe any ecc module in verilog. Indeed, I have to get a better understanding about ecc.

So please show me some links dealing with ecc theory in detail. I will appreciate to you greatly!

 

[tongson]

You can try to do a real project on the EV borad.

Or you can read the application notes on the xilinx website.

 

[bibo1978]

you have to decide first what is the ECC kind you want, convolution or block code, then the algorithm, like Viterbi algorithm then go ahead and start to implement the design if you have enough background in the Verilog

thats all folks