anybody suggestion on power management on chip

[berryfan]

i designed power management on SOC ,it include bandgap ,LDOs for RF and digital,so I think it's important to simulation of trans-response ,especially in digital and RF power management.
for example:when power on ,is there an large current i must be to provide to digital circuit.so my digital power management must can be provide large current in transient state.
other suggestions in power management ?thanks very much.

 

[girih192002]

Did you use enable circuitry to disable band gap reference, LDO of any RF or Digital when any one of it you do not required ?. it is possible way to minimize power consumption of Power IC.

if, you are gonna connect this Power IC with Li Battery then please try to go through National Semiconductor's application note on Power IC. it must give you more insight on Power IC.

 

[berryfan]

thanks very much,but there is another important question:
in power management ,when the LDO has empty load(no load current ),my LDO phase margine is 2degree.when has load(for example typical 1K)is 67degree.
have i must adjust my LDO (when empty load) phase margine is more than 70degree?
it must will decrease my speed

 

[girih192002]

When there is no load then. it means you are pumping maximum current to consecutive circuits and you have close loop phase margin around 2 degree. does your LDO is stable ?

I believe you need to increase its phase margin @ no load and @ full load. to avoid unstability.


to clear all your quesiton regarding you go through Dr. Rincon Mora's PhD thesis on LDO.

https://users.ece.gatech.edu/~rincon/

if you have any more question about Power Management then feel free to discuss with me. I am work in power management group. I want to be grow a expert in it. & I m very interested in Power IC stuff and Analog IC.

by take care

 

[berryfan]

thanks so much ,girih! i'm totally agree with your point ,i must improve it . in my circuit there is more than two zero point. so it's very dangerous to design. can i connect with you? my email is in_twos@163.com.thanks again~

 

[berryfan]

now i have something to ask :must i keep the LDO phase margine is ok?(from 0mA to my max mA),Ihad red some paper,it just from 1mA to 20mA,not from 0mA.

 

[girih192002]

now i have something to ask :must i keep the LDO phase margine is ok?(from 0mA to my max mA),Ihad red some paper,it just from 1mA to 20mA,not from 0mA.

you mean, when we talk about no load condition.then, we should not talk like 0 mA current (@ no load) .

is that you question?

 

[berryfan]

i mean ,when we design an LDO,Do we need to consider the conditon(0mA load current)?
hah

 

[dhasmana]

If the condition (0mA) current is possible then you have to consider that condition also. In any case , you need to ensure the stability for 0mA load current also.

 

[frankliner]

You do not need to consider 0mA if the condition can not occur. This depends on the system spec. I have once added a 1mA current source which switched off when the external load was increased.

 

[berryfan]

in my system.it just a transient 0mA current load.it happens when my LDO is working ,then after several us my load current can increase a value.it just a very short time.must I consider this condition?

 

[berryfan]

that is to say:what standard to justify the min-max current.for example:in VDD transit simulation,the maxim current is 30mA which is appear at start .so the max current is 30mA?
thanks all of you

 

[berryfan]

how can I compensation LDO,when load current 0~20mA

 

[girih192002]

how can I compensation LDO,when load current 0~20mA

to compensate, I believe you must have off chip bypass capcitor and load capacitor. it will give you two poles and one zero and one pole will generate by Error amplifier and pass transistor capacitor.

Could you tell me how many pole and zero do you have in your LDO close loop ?

 

[berryfan]

3poles and 1zero，the second pole is load pole which changing by load current

 

[girih192002]

3poles and 1zero，the second pole is load pole which changing by load current

could you tell me position of pole and zero in circuit:

P1 = 1/ 2*pe*Ropass*Co
P2=1/ 2*pi*Resr*Cb
P3= 1/ 2*pe*Roa*Cpar


analyse your bode plot and see are you getting same as above:

if possible can you post your circuit diagram

I will try to help more in detail
I have designed silicon LDO on 180 nm for 50 ~ 90 mA output current with 2 % accuracy.

 

[indianece]

We can able implement power management on chip technique into base stations . for power management in BTS

plz advise