anybody let me know the estimateted parameters of TSMC0.18?

[yonzzan]

mm_non-epi

I need to find hand calculation parameters such as 1) lambda, 2) UCox, 3) Vth, for W/L=2/.18, 2/.36, 2/.54 and 2/.72um. Since it takes so long to get all the value by simulating with cadence, I will really appreciate if anyone who has already done that can give me the values.

Thank you very much.

 

[Mistico_Pereyra]

tsmc018 model

There are several types of processes of this technology, you can get the information at:

https://www.mosis.com/products/fab/vendors/tsmc/tsmc018/

the Parametric Test Results and SPICE Model Parameters:
https://www.mosis.com/products/fab/vendors/tsmc/tsmc018/


the files are like this:

MOSIS WAFER ACCEPTANCE TESTS

RUN: T68B (MM_NON-EPI) VENDOR: TSMC
TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns
Run type: SKD


INTRODUCTION: This report contains the lot average results obtained by MOSIS
from measurements of MOSIS test structures on each wafer of
this fabrication lot. SPICE parameters obtained from similar
measurements on a selected wafer are also attached.

COMMENTS: DSCN6M018_TSMC


TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL UNITS

MINIMUM 0.27/0.18
Vth 0.50 -0.51 volts

SHORT 20.0/0.18
Idss 547 -250 uA/um
Vth 0.51 -0.51 volts
Vpt 4.8 -5.6 volts

WIDE 20.0/0.18
Ids0 14.4 -4.7 pA/um

LARGE 50/50
Vth 0.43 -0.42 volts
Vjbkd 3.1 -4.3 volts
Ijlk <50.0 <50.0 pA

K' (Uo*Cox/2) 175.4 -35.6 uA/V^2
Low-field Mobility 416.52 84.54 cm^2/V*s

COMMENTS: Poly bias varies with design technology. To account for mask
bias use the appropriate value for the parameters XL and XW
in your SPICE model card.
Design Technology XL (um) XW (um)
----------------- ------- ------
SCN6M_DEEP (lambda=0.09) 0.00 -0.01
thick oxide 0.00 -0.01
SCN6M_SUBM (lambda=0.10) -0.02 0.00
thick oxide -0.02 0.00


FOX TRANSISTORS GATE N+ACTIVE P+ACTIVE UNITS
Vth Poly >6.6 <-6.6 volts



PROCESS PARAMETERS N+ P+ POLY N+BLK PLY+BLK M1 M2 UNITS
Sheet Resistance 6.7 7.8 8.0 59.7 313.6 0.08 0.08 ohms/sq
Contact Resistance 10.6 11.0 10.0 4.79 ohms
Gate Oxide Thickness 41 angstrom

PROCESS PARAMETERS M3 POLY_HRI M4 M5 M6 N_W UNITS
Sheet Resistance 0.08 0.08 0.08 0.03 930 ohms/sq
Contact Resistance 9.24 14.05 18.39 20.69 ohms

COMMENTS: BLK is silicide block.


CAPACITANCE PARAMETERS N+ P+ POLY M1 M2 M3 M4 M5 M6 R_W D_N_W M5P N_W UNITS
Area (substrate) 942 1163 106 34 14 9 6 5 3 123 125 aF/um^2
Area (N+active) 8484 55 20 13 11 9 8 aF/um^2
Area (P+active) 8232 aF/um^2
Area (poly) 66 17 10 7 5 4 aF/um^2
Area (metal1) 37 14 9 6 5 aF/um^2
Area (metal2) 35 14 9 6 aF/um^2
Area (metal3) 37 14 9 aF/um^2
Area (metal4) 36 14 aF/um^2
Area (metal5) 34 984 aF/um^2
Area (r well) 920 aF/um^2
Area (d well) 582 aF/um^2
Area (no well) 137 aF/um^2
Fringe (substrate) 212 235 41 35 29 21 14 aF/um
Fringe (poly) 70 39 29 23 20 17 aF/um
Fringe (metal1) 52 34 22 19 aF/um
Fringe (metal2) 48 35 27 22 aF/um
Fringe (metal3) 53 34 27 aF/um
Fringe (metal4) 58 35 aF/um
Fringe (metal5) 55 aF/um
Overlap (N+active) 895 aF/um
Overlap (P+active) 737 aF/um



CIRCUIT PARAMETERS UNITS
Inverters K
Vinv 1.0 0.74 volts
Vinv 1.5 0.78 volts
Vol (100 uA) 2.0 0.08 volts
Voh (100 uA) 2.0 1.63 volts
Vinv 2.0 0.82 volts
Gain 2.0 -23.72
Ring Oscillator Freq.
D1024_THK (31-stg,3.3V) 300.36 MHz
DIV1024 (31-stg,1.8V) 363.77 MHz
Ring Oscillator Power
D1024_THK (31-stg,3.3V) 0.07 uW/MHz/gate
DIV1024 (31-stg,1.8V) 0.02 uW/MHz/gate

COMMENTS: DEEP_SUBMICRON




 T68B SPICE BSIM3 VERSION 3.1 PARAMETERS

SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8

* DATE: Oct 24/06
* LOT: T68B WAF: 6001
* Temperature_parameters=Default
.MODEL CMOSN NMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 2.3549E17 VTH0 = 0.3636291
+K1 = 0.5838101 K2 = 4.127489E-3 K3 = 0.6404026
+K3B = 2.5713333 W0 = 1E-7 NLX = 1.753559E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 1.3052219 DVT1 = 0.4111179 DVT2 = 0.0551704
+U0 = 266.1107358 UA = -1.419895E-9 UB = 2.352139E-18
+UC = 6.565935E-11 VSAT = 9.429196E4 A0 = 1.7723579
+AGS = 0.4051668 B0 = 7.941838E-8 B1 = 3.005112E-6
+KETA = -5.407505E-3 A1 = 0.5204773 A2 = 1
+RDSW = 130.8061518 PRWG = 0.4278613 PRWB = -0.2
+WR = 1 WINT = 0 LINT = 1.620242E-8
+XL = 0 XW = -1E-8 DWG = -8.056812E-9
+DWB = 6.598758E-9 VOFF = -0.0964987 NFACTOR = 2.4197852
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 2.810394E-3 ETAB = 3.137621E-6
+DSUB = 0.0115258 PCLM = 0.6875531 PDIBLC1 = 0.1251592
+PDIBLC2 = 2.98914E-3 PDIBLCB = -0.1 DROUT = 0.7011372
+PSCBE1 = 8E10 PSCBE2 = 1.721793E-9 PVAG = 1.067213E-3
+DELTA = 0.01 RSH = 6.7 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 8.95E-10 CGSO = 8.95E-10 CGBO = 1E-12
+CJ = 9.515702E-4 PB = 0.8 MJ = 0.3779345
+CJSW = 2.561363E-10 PBSW = 0.7 MJSW = 0.1167351
+CJSWG = 3.3E-10 PBSWG = 0.7 MJSWG = 0.1167351
+CF = 0 PVTH0 = -1.184709E-3 PRDSW = -2.3246954
+PK2 = 6.277782E-4 WKETA = 2.881549E-4 LKETA = -8.990893E-3
+PU0 = 7.0240127 PUA = 1.149338E-11 PUB = 0
+PVSAT = 1.587169E3 PETA0 = 1E-4 PKETA = 8.490252E-4 )
*
.MODEL CMOSP PMOS ( LEVEL = 49
+VERSION = 3.1 TNOM = 27 TOX = 4.1E-9
+XJ = 1E-7 NCH = 4.1589E17 VTH0 = -0.3932705
+K1 = 0.5903025 K2 = 0.0219618 K3 = 0.0995693
+K3B = 5.8822409 W0 = 1E-6 NLX = 1.195759E-7
+DVT0W = 0 DVT1W = 0 DVT2W = 0
+DVT0 = 0.6188318 DVT1 = 0.2460174 DVT2 = 0.1
+U0 = 110.5057255 UA = 1.377621E-9 UB = 1.271816E-21
+UC = -1E-10 VSAT = 1.131497E5 A0 = 1.5988581
+AGS = 0.3352489 B0 = 2.189139E-7 B1 = 9.37713E-7
+KETA = 0.0221995 A1 = 0.8 A2 = 0.4421783
+RDSW = 223.7367117 PRWG = 0.5 PRWB = -0.0576591
+WR = 1 WINT = 0 LINT = 2.949516E-8
+XL = 0 XW = -1E-8 DWG = -3.223729E-8
+DWB = -1.652628E-8 VOFF = -0.0923334 NFACTOR = 1.9212866
+CIT = 0 CDSC = 2.4E-4 CDSCD = 0
+CDSCB = 0 ETA0 = 0.101736 ETAB = -0.0229142
+DSUB = 0.8849034 PCLM = 2.4031621 PDIBLC1 = 2.393944E-4
+PDIBLC2 = 0.0227249 PDIBLCB = -7.281329E-4 DROUT = 9.989608E-4
+PSCBE1 = 1.723722E9 PSCBE2 = 5E-10 PVAG = 14.9986042
+DELTA = 0.01 RSH = 7.8 MOBMOD = 1
+PRT = 0 UTE = -1.5 KT1 = -0.11
+KT1L = 0 KT2 = 0.022 UA1 = 4.31E-9
+UB1 = -7.61E-18 UC1 = -5.6E-11 AT = 3.3E4
+WL = 0 WLN = 1 WW = 0
+WWN = 1 WWL = 0 LL = 0
+LLN = 1 LW = 0 LWN = 1
+LWL = 0 CAPMOD = 2 XPART = 0.5
+CGDO = 7.37E-10 CGSO = 7.37E-10 CGBO = 1E-12
+CJ = 1.145174E-3 PB = 0.8549847 MJ = 0.4215146
+CJSW = 2.482114E-10 PBSW = 0.9320898 MJSW = 0.3003922
+CJSWG = 4.22E-10 PBSWG = 0.9320898 MJSWG = 0.3003922
+CF = 0 PVTH0 = 3.295296E-3 PRDSW = 6.6024854
+PK2 = 2.247694E-3 WKETA = 0.0236668 LKETA = 1.429876E-3
+PU0 = -1.6090985 PUA = -5.69245E-11 PUB = 1.424391E-22
+PVSAT = 50 PETA0 = 1E-4 PKETA = -3.486553E-3 )

 

[gingerjiang]

spice parameters for scn6m_subm process

you can simulate the operational point of the devices in cadence.
firstly, construct a circuit consisting of the measured transistor and several dc voltage sources, using these sources to set the transistor's operational point;
then, in dc analysis select "save the op point", and make dc analysis;
finally, show the transistor's dc operational point, you can find the transistor's parameters.
for uCox, use effbeta/(w/l)
for lambda, use 1/(ron*I)
for vth, it is showed directly