anybody knows about reltol, abstol ?

[aredhel_vlsi]

Hello, does anybody know about reltol (relative tolerance) and abstol? where do we set or check that? should I look for it at the anasimhelp file? cause what I've found there doesn't help.. I just want to check some errors at my simulations. I hope you get me.

 

[dick_freebird]

They are solution constraints on the simulator and will
have default variable values set, but you should be
able to bump them around as any other variable (in
a SPICE) or at least via some option menu (like
Spectre). What particular simulator?

There are more than RELTOL and ABSTOL, I have
also seen CHGTOL (good for circuits that -need- to
have accurate charge conservation) and VNTOL
for fine node voltage tolerances, TRTOL for transient
accuracy and so on.

In Cadence you may find what you're looking for in
the Choose Analyses, pick analysis, then look for an
Options button at the bottom of each analysis form.

 

[aredhel_vlsi]

You are quick! Well, I picked a Vdc analysis or a temperature analysis, but in the options I can see "State file parameters", "Output parameters", "convergence parameters" and "annotation parameters". I didn't notice anything like reltol or something.. is it up to the version of the technology? cause I use the version 6 .

 

[dick_freebird]

I think most of what I remember, is from the old
cdsSpice (SPICE2G6++) days; looking at my current
session I also do not see the "old favorites", just a
few "lumped" Accuracy Defaults in the tran chooser
and nothing underneath the Options that looks any
good.

Now you've got me wondering, just what sort of accuracy
Spectre bothers to try for.

In my present spectre.out I see this, some of your
tolerance variables are echoed:

Important parameter values:
start = 0 s
outputstart = 0 s
stop = 20 us
step = 20 ns
maxstep = 400 ns
ic = all
skipdc = no
reltol = 1e-03
abstol(I) = 1 pA
abstol(V) = 1 uV
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = moderate
method = traponly
lteratio = 3.5
relref = sigglobal
cmin = 0 F
gmin = 1 pS
maxrsd = 0 Ohm
mos_method = s
mos_vres = 50 mV


So they are indeed set somewhere. But I added reltol
to the Analog Environment variables list and set to
1E-4 (rather than 1E-3) and it still says 1E-3.


In the input.scs file I see, near the bottom:

simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
dochecklimit=yes checklimitdest=both

Perhaps you can either manually edit the input.scs
(or whatever it turns into just prior to being run),
or the header / footer files if you can find those. A
spectre.sim file seems to declare several:

$ more spectre.sim
// Spectre Analyses and Output Options Statements

// Output Options
simOptions options
//+ reltol = 1.00000000E-03
//+ vabstol = 1.00000000E-06
//+ iabstol = 1.00000000E-12
//+ temp = 27
//+ save = allpub
//+ currents = selected

// Analyses
// dc1 dc oppoint=logfile homotopy=all
// tran1 tran stop=1 errpreset=moderate

 

[aredhel_vlsi]

hmmm... ok I found the input.scs and spectre.sim, except spectre.out and I found similar numbers to yours.(reltol=1e-03)

My temperature dc analysis is like the following diagram. As you see, the error is 5%, which is not satisfying to design a bandgap reference voltage. I want to see if I can change some values, in reltol to optimize my graph values and have a small deviation. Can I do that with reltol or abstol, or am I in a wrong way? Can I set it from somewhere else?

ps; I tried to change the reltol and abstol from the above files, I saved it, but the graph didn't change.

any suggestion?
thanks anyway

 

[dick_freebird]

That's a normal-appearing bandgap tempco, for a
design that has not been balanced (you need more
diode voltage and less resistor voltage). The tolerances
probably aren't significant to the solution, not relative
to the design values anyway.

 

[aredhel_vlsi]

Well, from what I've noticed in projects , the error in Vdc is usually 0.5 % to 1 %, then I have to do something to change that. I know I have to optimize the design of the schematic (like the following), although I tried to add diode connected bipolar transistors and could not decrease the deviation. Additionally ,that increases the layout size too.
that's why I wanted to check what happens with reltol, in case it is to blame for my curve deviation..

as far as I can see you know bandgap subjects, can I ask how big P consumption should I expect? I noticed 500 uA at a 1.8 Vdc. It's a lot isn't it?

 

[dick_freebird]

That's larger than I would want, and you may see
the tempco improve by changing the bias setpoint
lower.

You kind of have to "take what you get" for voltage,
if you want tempco right. Some process' diodes may
give you 1.25V while another's gives you 1.21 for
the "magic" voltage. You can tweak with number of
diodes (ratio) and so on. But if you reall, really need
dead-nuts 1.250V you may have to do things like a
buffered output w/ divider, or something. Usually for
a standard analog cell design, you just document what
the voltage happens to be, with flat TC, and use that
value in setting up other feedback ratios, etc.

CMOS bandgaps can be run nelow 10uA though for my
uses I prefer maybe 50uA, this gives a little better
matching (further away from a variable SOI leakage
floor, etc.) and tightness of distribution.

 

[aredhel_vlsi]

oups! I think you answered while I was posting my new question!

That's larger than I would want, and you may see
the tempco improve by changing the bias setpoint
lower.

how will I change that?i don't get you.

you just document what
the voltage happens to be, with flat TC

you mean estimate? from the documentation? somebody told me I should expect 1.25 V but why?

CMOS bandgaps can be run nelow 10uA though for my
uses I prefer maybe 50uA, this gives a little better
matching

you mean the total current that the Vdc source consumes , right? oh god then I have huge problem! you see, I can not drop it under 300uA !