Jan 16, 2003 #1 O Ohh Member level 2 Joined May 31, 2001 Messages 50 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 440 Xilinx's Forge is a behavioral compiler that can generate RTL verilog code from Java byte code, which can be implemented in a Xilinx FPGA. **broken link removed**
Xilinx's Forge is a behavioral compiler that can generate RTL verilog code from Java byte code, which can be implemented in a Xilinx FPGA. **broken link removed**
Jan 16, 2003 #2 O Ohh Member level 2 Joined May 31, 2001 Messages 50 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 440 Here are some PDF files about Xilinx Forge compiler.
Jan 16, 2003 #3 E eman Member level 1 Joined Jun 23, 2001 Messages 33 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 165 That sounds very good, has anyone here used it? please give some comments on the compiler. eman
Jan 16, 2003 #4 T telecom Junior Member level 1 Joined Jan 1, 2003 Messages 16 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 86 Celoxica DK1.1 also does the similar job but using Handel-C code !
Jan 16, 2003 #5 O Ohh Member level 2 Joined May 31, 2001 Messages 50 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,286 Activity points 440 JHDL is another academic tool that can synthesize an FPGA netlist from Java bytecode.
Mar 31, 2003 #6 2 2heat Junior Member level 2 Joined Mar 21, 2003 Messages 20 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 143 Forge Hi, does anyone have any docu about forge ... which java expression need to b used to generate special HW segments ... the docu with forge from X@l@nx is not so much ... Thankx heat
Forge Hi, does anyone have any docu about forge ... which java expression need to b used to generate special HW segments ... the docu with forge from X@l@nx is not so much ... Thankx heat