Any problem with this bias condition ? (OPAMP)

As guys you can see in the attached diagram , I wanna bias my positive input terminal with a half supply (vdd/2) voltage. And it's DC blocked from the external positive input, the input resistance of amplifier needed to be very large (>100Mohm), so basically R-R is not a solution since it cost too much area. I need to know if two set of Back to Back diodes (PN diode, P+ and N-well)like this connection could be used (only nA current flow) to provide the half supply voltage and also achieve high impedance since it's nA operation (one is reverse biased,only leakage current). It seems good in simulation, but any issue needed to be concerned ???

The opamp is used as a non-invertering amplifier with a high pass function.

Even though the diode connection may work in simulation, it still has lots of issues: the leakage current varies with temperature, they are also poorly modeled in many process, etc.

If you want a more reliable design and better control of the input DC bias level (i.e. VDD/2), you can use a more advanced design: use one current source and one current sink connected between VDD and ground. Their central point, denoted as VA, can be tied to an auxiliary amplifier's positive input terminal. This aux OTA's negative input can be biased at VDD/2. The output of this OTA will control the upper current source to form a close loop. If the loop gain is sufficient, with certain compensation capacitor to ensure stability, you can have a very good, precisely controled DC input voltage needed for your main opamp.

I forgot to say I have another concern which is about noise performance. My input better be noise free. Besides, add an aux amplifier might cost too much current consumption. Do you have any reference design (or ref. paper) which is about what you mentioned in the reply ?

You can try MOSFETs in diode configuration with huge Ls and very small W's. You can put a lot of them in series to get the required resistance and the low current.

Okay. My design cares much in low frequency noise. Especially for flicker noise. And I was just wondering if diode-connected MOS get more flicker noise than PN diodes ? .. Also my vdd ranges from 1.5 ~ 5.5V, NP diode connected may not achieve the half vdd precisely

Anyone can give further suggestion ?

I didn't see any problem using dioded-connected Tx to bias the circuit, it should work fine for getting Vdd/2, as for noise performance, I you can make WL large.

I will take back what I proposed the other day: the close loop configuration will give you an accurate DC bias level at the OTA non-inverting terminal, but the impedance will be too low to satisfy your requirement, due to the existance of the feedback network.

All really comes down to the trade off you have to make in every day: DC accuracy and impedance level. You may be able to get the high impedance level you want, but you can not have the desired VDD/2 DC level close to what you want. In your appliation, the accruacy of the DC level is not that critical as long as your common-mode input level makes your Opamp happy. Thus I suggest you relax the DC bias level accuracy to get the desired impedance level to fulfil your high pass filter corner frequency requirement.

What I used in this design are PN diodes, not diode connected MOS transistors. Large W and L can bring me the lower noise, but it brings large input capacitance too. And this may degrade the input signal very much. So I just wonder if I should take care of the flicker noise in PN diodes ? Since
I don't get much sense on the noise for diodes. Just like what you mentioned, I think DC accuracy is not that critical for me.
What I need is actually a low noise (@ low frequency), high impedance (both resistance and capacitance) DC bias stage for my operation amplifier . Any other way to implement the given requirement .

Your back-2-back diode needs a discharging path. The way u connect them could end up with some junction breakdowns. Basically, u have a rectifier. Any capacitive coupling could pull the node b/w the B2B diodes high enough to cause the P+ to Nwell to breakdown.
U need to clamp that node.
Also, noise at low frequency is not an issue as u r building a high pass.
What's your driving source for this HPF?
IF u have a really low drive source driving this input, i suggest u buffer the signal first, u may not need to insert a full fledge opamp buffer. some simple modification to your source output stage could do. This way, u could do away with pn, and use a resistor, which is much more problem free.
And u need to check for latch up path when it comes to layout if u decide to stick to your original design.

Added after 3 minutes:

Your back-2-back diode needs a discharging path. The way u connect them could end up with some junction breakdowns. Basically, u have a rectifier. Any capacitive coupling could pull the node b/w the B2B diodes high enough to cause the P+ to Nwell to breakdown.
U need to clamp that node.
Also, noise at low frequency is not an issue as u r building a high pass.
What's your driving source for this HPF?
IF u have a really low drive source driving this input, i suggest u buffer the signal first, u may not need to insert a full fledge opamp buffer. some simple modification to your source output stage could do. This way, u could do away with pn, and use a resistor, which is much more problem free.
And u need to check for latch up path when it comes to layout if u decide to stick to your original design.