achaleus
Member level 5
Dear edaboard,
While designing a cache we should satisfy the condition
cache size <= BLOCK size * set associativity, if we increase cache size or by decreasing associativity we ran into aliasing problem.
there are very less information available regarding overcoming aliasing (anti aliasing hardware), any papers eliminating this issues are most welcome.
many cache designs generally have 16kb 2 way I-cache and 32KB 4-way D-cache designs, but how they are eliminating aliasing (considering not every OS do page coloring and supports only 4KB pages) in cache design.
Thank you,
Vinay
While designing a cache we should satisfy the condition
cache size <= BLOCK size * set associativity, if we increase cache size or by decreasing associativity we ran into aliasing problem.
there are very less information available regarding overcoming aliasing (anti aliasing hardware), any papers eliminating this issues are most welcome.
many cache designs generally have 16kb 2 way I-cache and 32KB 4-way D-cache designs, but how they are eliminating aliasing (considering not every OS do page coloring and supports only 4KB pages) in cache design.
Thank you,
Vinay
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