Re: antenna vilation
Hi Jitu,
1) On which parameters any body will decide whether he has to do metal jogging or diode insertion? Does these instructions comes from top level designer?
If you want to know what is antenna violation ?, please go through a ASIC book or literature. that should help us to get the idea
which parameter decides : -> It is ratio of Metal area by Gate area of transistor. ( to know why, literature on ASIC should help u)
from where this comes : --> all the foundaries will give a rule deck for Antenna DRC violation. they will check the ratio (defined in above line) by coding it as rule in drc deck itself
2) Why we always do metal jogging to upper metal layers only, why not to lower layers?
Resistivity of lower layer will be high, so if we jog to lower layers , we will actually increase the resistance of the net, so by solving the problem of Antenna violation , we will tend to increase the delay of net. but jogging to higher layer will not increase net resistance.
3) What is the speciality of antenna diode? Is this the ordinary diode or some special diode?
nothing special, they are simple reverse biased diodes but made of transistors
4) If any body is facing antenna violation in top most layer say M8 then how will he remove this violation because then there is no option for metal jogging because M8 itself is topmost layer.
it cant be solved, that is why people dont use top metal for signal routing
Hope it helps u
Regards
Nav