Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Antenna rules in GF 45 RFSOI

Status
Not open for further replies.

big_fudge98

Member level 2
Member level 2
Joined
Mar 31, 2019
Messages
43
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
445
Hi,

I have a question about resolving antenna errors in GF45RFSOI process.
I could not find any antenna diodes in this process. So for resolving antenna errors, I added a 'bitieres'. From what I understand, bitieres is a contact from M1 to the substrate. So if we use bitieres for multiple nets, will they not create a short through the substrate? Or is the substrate resistance high enough, so that this short will not cause issues?

Thanks
 

SOI is a tough problem for antenna because there may be either no handy place to grab a global substrate tap, or the "web" (front side silicon with no device layers) must be tied to make it so.

Antenna diode is just a minimum diode, whether the kit supports diodes in the core you'd have to investigate. If not then a minimum GG NMOS dummy's drain would do. Fin type technologies have a fixed pattern in the lower layers and wouldn't allow random placement of taps and antenna diodes other than can be made by a fin segment.
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top