Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

And gate using pn diodes

Status
Not open for further replies.

Damomeera

Junior Member level 3
Junior Member level 3
Joined
Nov 11, 2012
Messages
30
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Coimbatore
Activity points
1,506
see the circuit diagram in the following link:

www.asic-world.com/images/digital/gates_and_2rtl.gif

If X = 0 and Y = 0, then both diodes D1 andD2 are forward biased and thus both diodes conduct and pull F low. If X = 0 and Y = 1, D2 is reverse biased, thus does not conduct. But D1 is forward biased, thus conducts and thus pulls F low. If X = 1 and Y = 0, D1 is reverse biased, thus does not conduct. But D2 is forward biased, thus conducts and thus pulls F low. If X = 1 and Y = 1, then both diodes D1 andD2 are reverse biased and thus both the diodes are in cut-off and thus there is no drop in voltage at F. Thus F is HIGH.
 

Commenting on your explanation.
With any input at 0 you will get approx .7v (diode forward drop) at the output. .For both inputs high you get a high on the output pin. In that case the output voltage will be .7v+the lower of the 2 input voltages (up to a max of VCC).
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top